標題: A 1-100Mb/s 0.5-9.9mW LDPC Convolutional Code Decoder for Body Area Network
作者: Chen, Chih-Lung
Wu, Sheng-Jhan
Chang, Hsie-Chia
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2014
摘要: A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1 similar to 100Mb/s with power consumption of 0.5 similar to 9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.
URI: http://hdl.handle.net/11536/135869
ISBN: 978-1-4799-4089-9
期刊: 2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)
起始頁: 229
結束頁: 232
顯示於類別:會議論文