適用於行動式全球互通微波存取通訊協定之2.37Gb/s LDPC-CC 編解碼器設計

Abstract

行動通訊系統中，通道編解碼模組往往扮演關鍵角色，不僅要達到高吞吐量的傳輸需求，也必須降低伴隨而來的功率消耗，以提供具有技術競爭力的解決方案。低密度奇偶校驗區塊碼(LDPC block codes，簡稱LDPC-BCs)因具有優越的錯誤更正能力與適合平行運算之架構而廣受矚目，然而，此解碼器在實作時面臨高繞線複雜度的困難，在設計支援多碼率之LDPC-BCs也面臨許多挑戰。低密度奇偶校驗迴旋碼（LDPC convolutional codes，簡稱LDPC-CCs）於1999年提出，此碼可對任意長度的資料區塊做編解碼，且易於經由穿孔(puncturing)機制提供彈性的碼率。相較於傳統LDPC-BCs，LDPC-CCs具有簡單的編碼電路及較低的繞線複雜度，相較於渦輪碼(Turbo codes)，更易於實現高速解碼器架構並且降低功率消耗。

近來，IEEE制定新一代無線寬頻技術標準802.16m，又稱為行動式全球互通微波存取通訊協定(Mobile WiMAX)，提供更高的資料傳輸速率和較低的延遲以滿足下世代行動通訊，雖然LDPC-CCs具有符合未來傳輸需求的潛力，但目前卻因解碼延遲過高、解碼吞吐量偏低、功率消耗過高等困難而尚未被通訊標準採用。據此，本作品提出演算法、節點、位元等三個層級的最佳化架構來提升吞吐量、減少硬體花費及降低解碼延遲時間，並藉由混合分割式FIFO架構來降低功率消耗。此論文使用Panasonic針對802.16m標準所提出之提案中的規格來實作，一個碼率相容(rate compatible)週期為3之LDPC-CC。演算法層級最佳化使用即時變數節點激活並隱藏通道值之解碼排程(on-demand variable node activation scheduling with concealing channel values)可加快一倍的解碼收斂速度，並省去17%的暫存器使用量，節點層級最佳化使用暫存器摺疊法(Folding architecture)可將平行度提高到12，並同時降低解碼延遲12倍，經由時序重排(Retiming)進一步減少所需位元儲存量，最後使用混合分割式FIFO (Hybrid-partitioned FIFO)來實現同時具有高吞吐量且低功率消耗之解碼器架構。

經由UMC 90 nm製程下線，在1.2V電壓下晶片實際量測到198 MHz，資料吞吐量高達2.37 Gbps，解碼器共包含5個處理器，在整體晶片面積2.7mm2中僅佔2.24 mm2，功率消耗為284mW，能源效率為0.024 nJ/bit/proc。所提出的解碼器在各方面都具有極高的競爭力，相當適合於未來使用手持行動裝置的高速網路傳輸需求。

In mobile communication system, channel coding modules play an important role. To provide a highly competitive solution, both high data-transmission rate and low power consumption are required. LDPC block codes (LDPC-BCs) has attracted great interest recently due to its capacity-approaching performance and inherent parallel architecture. However, the problem of high routing complexity becomes a design challenge in decoder implementations. The complexity of designing multiple code-rates LDPC-BCs is increased because of different parity-check matrices are needed to be jointly considered. Low-density parity-check convolutional codes (LDPC-CCs) were introduced in 1999, which are not only capable of handling variable length of data frame but also possess flexible code-rates. Compared with LDPC-BCs, LDPC-CCs enjoy the advantages of simple encoding circuitry as well as low routing complexity. Compared to the Turbo decoder, the LDPC-CC decoder is more suitable for highly-parallel implementation and low-power architecture.

Recently, IEEE 802.16m standards, also known as Mobile WiMAX Release 2.0, are developed in order to provide higher data rates and lower latency for next generation mobile communication systems. Although the LDPC-CC has the potential to meet the high-speed requirements for the next generation communication systems, it rarely appear in system specification for its bottlenecks of the long decoding latency, high power consumption, and low-to-moderate decoding throughput. Therefore, our work proposed three level optimization techniques, including algorithm-level, node-level and bit-level, to increase decoding throughput, lessen hardware costs, and reduce decoding latency. In particular, a hybrid-partitioned FIFO structure is presented to further reduce power consumption. We adopted the specification of rate-compatible (491, 3, 6) LDPC-CC with period of 3 proposed by Panasonic for the IEEE 802.16m standards. The on-demand variable node activation scheduling with concealing channel values is proposed for algorithm-level optimization. This technique not only allows twice faster decoding convergence speed than the standard decoding schedule, but also saves 17% message storage requirements. The node-level optimization enables the parallelism of 12, thus the throughput becomes twelve multiplying with clock frequency. In the meantime, the decoding latency is reduced by approximately 12 times. Also, the bit level optimization is utilized to retime the variable nodes in order to achieve higher clock frequency and around a 20% storage reduction.

Fabricated in UMC 90nm 1P9M CMOS process, the proposed LDPC-CC decoder chip could achieve maximum 2.37 Gb/s under 198MHz operating frequency. The decoder containing 5 processors only occupies an area of 2.24 mm 2 within the core area of total 2.37×1.14 mm2. It draws 284mW of power with an energy efficiency of 0.024nJ/bit/proc. Besides, the power can be scaled down to 90.2mW at 0.8V supply with 1.58Gb/s information throughput. In conclusions, our proposed LDPC-CC decoder outperforms state-of-the-art designs and is suitable for the high-speed requirements of next-generation handheld mobile devices.