使用重疊架構之超越Gb/s低密度同位元檢查迴旋碼解碼器設計

Abstract

在無線通訊系統中，通道編碼模組扮演重要的角色，為了提供具有技術競爭 力的解決方案，不僅需要達到高吞吐量傳輸也必須降低伴隨而來的功率消耗。由 於具有優越的錯誤更正能力與適合平行運算的架構，低密度奇偶校驗區塊碼 (LDPC block codes，簡稱LDPC-BCs)因而廣受矚目，然而此解碼器在實作時會面臨高繞線複雜度的問題。此外，在設計支援多碼率之LDPC-BCs 也面臨許多挑戰，低密度奇偶校驗迴旋碼（LDPC convolutional codes，簡稱LDPC-CCs）在1999年被提出，此碼不只可對任意長度的資料區塊做編解碼，而且容易經由穿孔(puncturing)機制提供彈性的碼率。相較於LDPC-BCs，LDPC-CCs 具有較低的繞線複雜度並且依然具有優秀的錯誤更正能力。 束縛長度長的LDPC-CC 會有好的錯誤地板現象，而且適合小錯誤率的應用，然而儲存單元的需求量會隨著記憶體容量成線性增加。為了克服此問題，本論文提出重疊架構不僅減少儲存單元的數量，也減少解碼延遲時間。此設計經由UMC65 nm 的低漏電製程下線，目前仍然還處於量測階段，從post-layout 模擬結果中，我們提出的解碼器在227 MHz 的操作頻率下，其資料吞吐量可達到5.44 Gb/s，其中包含5 個處理器，在整體晶片面積1.79 mm^2 中僅佔1.19 mm^2，功率消耗為195mW，能源效率為0.007 nJ/bit/proc。

In wireless communication system, the channel coding module play an important role. For providing a highly competitive solution, both high throughput transmission and low power consumption are required. Due to the capacity-approaching performance and inherent parallel architecture, LDPC block codes (LDPC-BCs) have attracted great interests in recent years. However, the problem of high routing complexity is a serious design challenge in VLSI implementations. Moreover, the complexity of designing multiple code-rates LDPC-BCs is increased because of different parity-check matrices are needed to be jointly considered. LDPC convolutional codes (LDPC-CCs) were introduced in 1999, which are not only capable of handling variable length of data frame but also possess flexible code-rates through puncturing. While performing the capacity-approaching performance, the routing complexity of the convolutional version is much lower than that of the LDPC-BCs. The long constraint length LDPC-CC has great error floor performance, which is very suitable for deep error rate applications. However, the requirement of the storage units grow large linearly according to the memory size. To overcome this problem, our work proposed the overlapped architecture to not only reduce the number of storage units but also decoding latency. The design is fabricated in UMC 65nm LL CMOS process and still under measurement. The post-layout simulations show that our proposed decoder could achieve 5.44 Gb/s under 227MHz operating frequency. The decoder containing 6 processors only occupies an area of 1.19 mm^2 within the core area of total 1.14*1.57 mm^2. It draws 195 mW of power with an energy efficiency of 0.007nJ/bit/proc.