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dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorWu, Sheng-Jhanen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2017-04-21T06:49:42Z-
dc.date.available2017-04-21T06:49:42Z-
dc.date.issued2014en_US
dc.identifier.isbn978-1-4799-4089-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/135869-
dc.description.abstractA low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1 similar to 100Mb/s with power consumption of 0.5 similar to 9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.en_US
dc.language.isoen_USen_US
dc.titleA 1-100Mb/s 0.5-9.9mW LDPC Convolutional Code Decoder for Body Area Networken_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)en_US
dc.citation.spage229en_US
dc.citation.epage232en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380484900058en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper