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dc.contributor.authorDhong, Sang H.en_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2017-04-21T06:48:56Z-
dc.date.available2017-04-21T06:48:56Z-
dc.date.issued2014en_US
dc.identifier.isbn978-1-4799-5127-7en_US
dc.identifier.issn2163-9612en_US
dc.identifier.urihttp://hdl.handle.net/11536/135886-
dc.description.abstractWe review advances in ASIC-compatible circuits for emerging SOC areas. These applications require ubiquitously low-power consumption during standby mode while providing a required performance in active mode. Sub- or near-threshold circuits may provide a low-power solution. However, they have yet to show how they fit into overall SOC optimization including area and performance. Selectively introducing custom-circuit techniques with ASIC tool compatibility have proven very attractive in reducing both the power and the area of a SOC by extending its Dynamic Voltage-Frequency Scaling (DVFS) range down to a VDD of 0.5 V.en_US
dc.language.isoen_USen_US
dc.subjectSOCen_US
dc.subjectASICen_US
dc.subjectDVFSen_US
dc.subject0.5V VDDen_US
dc.subjectPulse latchen_US
dc.subjectIOTen_US
dc.titleRecent Advances in ASIC-compatible Circuit Techniques for a SOC in Newly Emerging Application Areas: Invited Paperen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)en_US
dc.citation.spage24en_US
dc.citation.epage25en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000380406300024en_US
dc.citation.woscount0en_US
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