完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Dhong, Sang H. | en_US |
dc.contributor.author | Hwang, Wei | en_US |
dc.date.accessioned | 2017-04-21T06:48:56Z | - |
dc.date.available | 2017-04-21T06:48:56Z | - |
dc.date.issued | 2014 | en_US |
dc.identifier.isbn | 978-1-4799-5127-7 | en_US |
dc.identifier.issn | 2163-9612 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135886 | - |
dc.description.abstract | We review advances in ASIC-compatible circuits for emerging SOC areas. These applications require ubiquitously low-power consumption during standby mode while providing a required performance in active mode. Sub- or near-threshold circuits may provide a low-power solution. However, they have yet to show how they fit into overall SOC optimization including area and performance. Selectively introducing custom-circuit techniques with ASIC tool compatibility have proven very attractive in reducing both the power and the area of a SOC by extending its Dynamic Voltage-Frequency Scaling (DVFS) range down to a VDD of 0.5 V. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | SOC | en_US |
dc.subject | ASIC | en_US |
dc.subject | DVFS | en_US |
dc.subject | 0.5V VDD | en_US |
dc.subject | Pulse latch | en_US |
dc.subject | IOT | en_US |
dc.title | Recent Advances in ASIC-compatible Circuit Techniques for a SOC in Newly Emerging Application Areas: Invited Paper | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | en_US |
dc.citation.spage | 24 | en_US |
dc.citation.epage | 25 | en_US |
dc.contributor.department | 交大名義發表 | zh_TW |
dc.contributor.department | National Chiao Tung University | en_US |
dc.identifier.wosnumber | WOS:000380406300024 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |