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dc.contributor.authorZhao, Jun-Kaien_US
dc.contributor.authorChiu, Yi-Weien_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.contributor.authorChu, Yuan-Huaen_US
dc.date.accessioned2017-04-21T06:48:56Z-
dc.date.available2017-04-21T06:48:56Z-
dc.date.issued2014en_US
dc.identifier.isbn978-1-4799-5127-7en_US
dc.identifier.issn2163-9612en_US
dc.identifier.urihttp://hdl.handle.net/11536/135887-
dc.description.abstractIn this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V.en_US
dc.language.isoen_USen_US
dc.titleSubthreshold SRAM Macro Design with Pulse-Controlled Dynamic Voltage Scaling (PC-DVS)en_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)en_US
dc.citation.spage114en_US
dc.citation.epage115en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380406300052en_US
dc.citation.woscount0en_US
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