完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Zhao, Jun-Kai | en_US |
dc.contributor.author | Chiu, Yi-Wei | en_US |
dc.contributor.author | Jou, Shyh-Jye | en_US |
dc.contributor.author | Chu, Yuan-Hua | en_US |
dc.date.accessioned | 2017-04-21T06:48:56Z | - |
dc.date.available | 2017-04-21T06:48:56Z | - |
dc.date.issued | 2014 | en_US |
dc.identifier.isbn | 978-1-4799-5127-7 | en_US |
dc.identifier.issn | 2163-9612 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135887 | - |
dc.description.abstract | In this paper, we propose a pulse-controlled dynamic voltage scaling (PC-DVS) scheme in an SRAM macro to suppress leakage power consumption to reduce total power. The proposed SRAM macro is capable of operating in low-voltage regime with high variation immunity. The proposed PC-DVS scheme reduces the array power up to 62% at 500 kHz while the selected sub-bank operating at 0.5 V and the unselected sub-banks Hold data at 0.35 V. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Subthreshold SRAM Macro Design with Pulse-Controlled Dynamic Voltage Scaling (PC-DVS) | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2014 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | en_US |
dc.citation.spage | 114 | en_US |
dc.citation.epage | 115 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000380406300052 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |