標題: Investigation of Factors Affecting SET-Disturb Failure Time in a Resistive Switching Memory
作者: Su, P. C.
Chung, Y. T.
Chen, M. C.
Wang, Tahui
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: RRAM;SET-disturb failure time;cycling stress;resistance window;SET-disturb voltage
公開日期: 2016
摘要: Factors affecting SET-disturb failure time (tau(f)) in a tungsten oxide resistive switching memory including SET/RESET cycling stress, resistance window in operation and SET-disturb voltage are investigated. A SET-disturb failure time in high resistance state (HRS) may degrade by orders of magnitude in a post-cycling cell. The degradation is attributed to the formation of a current percolation path of cycling stress-generated traps. A one-dimensional percolation model is proposed for the tau(f) degradation. The dependence of tau(f) on resistance window in operation is characterized. We find that tau(f) is greatly affected by the current level of LRS. The strong LRS dependence of tf is attributed to a small Weibull slope of tau(f). In addition, we perform statistical characterizations of tau(f) at different SET-disturb voltages. A relationship between tau(f) and a SET-disturb voltage in a stressed cell is given.
URI: http://hdl.handle.net/11536/135897
ISBN: 978-1-4673-8833-7
ISSN: 2330-7978
期刊: 2016 IEEE 8TH INTERNATIONAL MEMORY WORKSHOP (IMW)
顯示於類別:會議論文