Efficient Digit-Serial Multiplier Employing Karatsuba Algorithm

Abstract

This paper presents a efficient digit-serial GF(2m) multiplier. The proposed architecture using digit-serial of concept to combine the principle of Karatsuba multiplier which can reduce circuit space complexity, also it is suitable for Elliptic Curve Cryptography (ECC) technology. We knows that the password system\'s operation core is a multiplier, however that password system\'s multiplier is very big, so it is necessary for reduce the area and time\'s complexity. This paper is implement three smaller multiplier and digit-serial in FPGA to reduce time and area complexity. This method uses 3dm/2 AND gate, 6 m + n+ 3dm/2 + m/2 + d-7 XORs and 3 m-3 registers. The paper using Altera FPGA Quartus II to simulate four different multipliers, 36 x 36, 84 x 84, 126 x 126 and 204 x 204, and implemented on Cyclone II EP2C70F896C8 experimental platform. The experimental results show that the proposed multipliers have lower time complexity than the existing digit-serial structures. The proposed architecture can reduce the time x space complexity decreasing when the bit-size of multiplier is increasing.