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dc.contributor.authorPreyss, Nicholasen_US
dc.contributor.authorSenning, Christianen_US
dc.contributor.authorBurg, Andreasen_US
dc.contributor.authorLiu, Wei-Changen_US
dc.contributor.authorLiu, Chun-Yien_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2017-04-21T06:48:24Z-
dc.date.available2017-04-21T06:48:24Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-7191-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/136012-
dc.description.abstractWe present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.en_US
dc.language.isoen_USen_US
dc.titleA 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nmen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC)en_US
dc.citation.spage193en_US
dc.citation.epage196en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380460000026en_US
dc.citation.woscount0en_US
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