十億級資料傳輸室內無線SC/OFDM接收機之等化器

Abstract

本論文針對IEEE 802.15.3c標準中的雙模式(單載波和正交分頻多工)提出適應性最小均平方(LMS)頻域等化器搭配最小平方(LS)頻域通道估測(LS-LMS FDE)，和多重路徑干擾消除(MPIC)時域等化器搭配格雷(Golay)序列時域通道估測(Golay-MPIC TDE)。此兩種方法皆可以共用雙模式中的硬體，以達到降低硬體複雜度的目的。LS-LMS FDE使用了最小均平方的適應演算法以及最小平方的通道估測來加速收斂速度同時也能保持低運算複雜度。模擬的結果顯示在訊雜比為12dB時，未具有任何編碼保護下的位元錯誤率，在單載波和正交分頻多工模式中，分別可達到6.01*10-4和9.68*10-3。整體的等效邏輯閘數除了快速傅立葉轉換模組外，為41.5萬個邏輯閘，其中有69%是雙模式共用的硬體。當操作頻率在400MHz時，不包含快速傅立葉轉換模組的功率消耗只有81.27毫瓦。而Golay-MPIC TDE使用多重路徑干擾消除演算法降低硬體複雜度及格雷序列通道估測來消除雜訊干擾。當訊雜比為12dB時，未具有任何編碼保護下的位元錯誤率，在單載波和正交分頻多工模式中，分別可達到2.53*10-4和4.22*10-5。整體的等效邏輯閘數為40.5萬個邏輯閘，其中有99%是雙模式共用的硬體。操作頻率在400MHz時，功率消耗只有88毫瓦。 本論文提出的頻域和時域等化器，分別整合進兩個室內無線傳輸基頻接收機中。基於高速和面積使用率的考量，硬體合成使用了65奈米1伏特1P9M CMOS製程。LS-LMS FDE晶片的核心部分占了7.81mm2，使用率是65.91%。操作頻率為333 MHz，資料傳輸率在單載波和正交分頻多工模式中，分別可達到3.52Gbps和5.28Gbps，功率消耗793.98毫瓦。符號邊界同步估測器與此LS-LMS FDE共用的記憶體佔了32.68%。而Golay-MPIC TDE晶片的核心部分占了7.95 mm2，使用率是88.93%。操作頻率為336.7 MHz，資料傳輸率在單載波和正交分頻多工模式中，分別可達到3.52Gbps和5.28Gbps，功率消耗為1.12瓦。符號邊界同步估測器、相位雜訊消除器與此Golay-MPIC TDE共用的記憶體佔了37%。

This thesis proposes an adaptive LS-LMS FDE and LOS Goaly-MPIC TDE that can satisfy the dual mode (SC and HSI) specifications of IEEE 802.15.3c. The hardware of both methods can be shared by SC and HSI mode to reduce hardware complexity. The LS-LMS FDE combines LMS adaptive algorithm with LS channel estimation. The LMS algorithm has the advantage of low computational complexity and sufficient convergence speed with the aid of LS channel estimation. The simulation results show that the LS-LMS FDE can achieve 6.01*10-4 BER in SC mode and 9.68*10-3 BER in HSI mode (both uncoded) at SNR 12 dB. The total area is about 415K gate-count with 69% shared among SC and HSI mode except 2 FFT. The power consumption excluding FFT is only 81.27 mW when working at 400MHz. On the other hand, the Golay-MPIC TDE uses Multi-path Interference Cancellation (MPIC) equalization with Golay sequence-aided channel estimation. The MPIC algorithm can reduce the hardware complexity unlike traditional time-domain equalizer and Golay sequence-aided channel estimation will eliminate the AWGN noise. The Golay-MPIC TDE can achieve 2.53*10-4 BER in SC mode and 4.22*10-5 BER in HSI mode (both uncoded) at SNR 12dB. The total area is about 405K gate-count with 99% shared by SC and HSI mode. The power consumption is only 88 mW when working at 400 MHz. The proposed different domain architectures are integrated in two indoor wireless communication baseband receiver systems. For the high speed and area efficiency considerations, the overall system designs are implemented using 65 nm 1P9M CMOS GP process under supply voltage 1.0 V. The LS-LMS FDE chip occupies 7.81mm2 core area with 65.91% utilization, and the clock rate is 333 MHz. The data rate of SC and HSI mode can achieve 3.52 Gbps and 5.28 Gbps, respectively. Also, the power consumption is 793.98 mW. The shared memory is 32.68% of the baseband system which is shared by BD and FDE blocks. The core area of Golay-MPIC TDE chip is 7.95 mm2 with 88.93% utilization, and the clock rate is 336.7 MHz. The data rate of SC and HSI mode can achieve 3.52 Gbps and 5.28 Gbps, respectively. Also, the power consumption is 1.12 W. The BD, TDE and PNC blocks use the same shared memory which is 37% of the baseband system.