應用於一百五十億位元室內無線 SC/OFDM接收機之等化器與基頻設計

Abstract

本論文提出針對IEEE 802.15.3c 標準設計與實作之單載波(SC)和正交多頻分工(OFDM)雙模無線基頻接收機，本無線基頻接收機主要包含五個主要功能性電路區塊，分別是前置碼(preamble)/符元(symbol)邊界偵測、取樣時脈飄移同步估測補償、載波頻率漂移同步估測補償、頻域等化器以及相位雜訊消除。本論文將關鍵之模組為兩種模式共用以達節省硬體複雜度以及降低功率消耗之目的。 此無線基頻接收機之等化器在架構上，利用新的通道估測演算法，窗戶式雜訊消除器，消除大部分雜訊對於估測通道的影響，取代適應性最小平均平方法(LMS)。並使用固定點數運算模擬、配合計算訊號量化雜訊比(SQNR)，使各個電路節點都使用最小浮點數運算。新的等化器利用經由此二種化簡法，共減少了整體邏輯閘數目41.5%。 整體無線基頻接收機系統電路操作頻率為400MHz，資料傳輸率在單載波和正交分頻多工模式中，分別可達到7.04Gbps 和15.84Gbps。硬體面積共243萬個等效邏輯閘，總功耗44毫瓦。在非直視通道(NLOS)環境，訊噪比(SNR)為12分貝(dB)的情況下，且未具有任何編碼保護下的位元錯誤率在單載波和正交分頻多工模式中，分別可達到6.01×10-4 和5.84×10-4。

This thesis proposes a single carrier (SC) and high speed interface (HSI) dual mode wireless receiver which is designed and implemented for IEEE 802.15.3c standard. There are five main block functional blocks in the baseband receiver as following: boundary detection, sampling clock offset (SCO) cancellation, carrier frequency offset (CFO) cancellation, frequency domain equalizer, and phase noise cancellation. The hardware of key modules between SC/HSI dual modes is shared to reduce the hardware complexity and power consumption. The baseband receiver adopts a new channel estimator, window-based noise cancellation (WNC) which can eliminate most noise of channel impulse response. Therefore, the LMS is replaced by WNC. Next, the fixed point simulation with calculating the signal to quantization error is used to minimize the word length of each point. With two methods above, the total gate count is reduced by 41.5%. The baseband receiver works at 400MHz. The data rate can achieve 7.04Gbps and 15.84Gbps in SC mode and HSI mode, respectively. The area is 243k gate count and the power is 44mW. In NLOS channel, the uncoded BER at SNR 12dB can achieve 6.01×10-4 and 5.84×10-4 in SC mode and HSI mode, respectively.