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dc.contributor.authorKuo, Bo-Jyunen_US
dc.contributor.authorChen, Bo-Weien_US
dc.contributor.authorTsai, Chia-Mingen_US
dc.date.accessioned2017-04-21T06:48:28Z-
dc.date.available2017-04-21T06:48:28Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4799-6275-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/136075-
dc.description.abstractThis paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=10(-9), the comparator achieves 143fJ at 3.3GHz and a 0.9V supply, which decreases to only 49fJ at 1.3GHz and a 0.6V supply. Both measured results are based on the input differential voltage of only 4.2mV. The comparator is implemented in 65nm CMOS technology and the chip area of the core circuit occupies 265 mu m(2).en_US
dc.language.isoen_USen_US
dc.titleA 0.6V, 1.3GHZ DYNAMIC COMPARATOR WITH CROSS-COUPLED LATCHESen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 International symposium on VLSI Design, Automation and Test (VLSI-DAT)en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000380584400030en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper