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dc.contributor.authorHu, Vita Pi-Hoen_US
dc.contributor.authorSu, Pinen_US
dc.contributor.authorChuang, Ching-Teen_US
dc.date.accessioned2017-04-21T06:49:47Z-
dc.date.available2017-04-21T06:49:47Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4799-9928-6en_US
dc.identifier.issn1946-1550en_US
dc.identifier.urihttp://hdl.handle.net/11536/136099-
dc.description.abstractThis paper investigates the impacts of negative and positive bias temperature instabilities (NBTI and PBTI) on the stability of ultra-thin-body (UTB) GeOI 6T SRAM cell and performance of sense amplifier compared with the SOI counterparts. Worst case stress scenarios for read and write operations are analyzed. For UTB GeOI SRAMs, PBTI dominates the degradations in read static noise margin (RSNM), while for UTB SOI SRAMs, NBTI dominates the degradations in RSNM. Write static noise margin (WSNM) only slightly degrades due to NBTI and PBTI. Current latch sense amplifier (CLSA) and voltage latch sense amplifier (VLSA) are analyzed considering NBTI/PBTI for GeOI and SOI devices. GeOI CLSA and VLSA show smaller word-line to SAE buffer delay (T-BL) and sense amplifier sensing delay (T-SA) than the SOI counterparts. As aging time increases, GeOI CLSA and VLSA show larger degradations of T-SA than the SOI counterparts.en_US
dc.language.isoen_USen_US
dc.titleUTB GeOI 6T SRAM Cell and Sense Amplifier considering BTI Reliabilityen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015)en_US
dc.citation.spage111en_US
dc.citation.epage114en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380466200030en_US
dc.citation.woscount0en_US
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