完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tsai, Jung-Ruey | en_US |
dc.contributor.author | Wen, Ting-Ting | en_US |
dc.contributor.author | Yang, Shao-Ming | en_US |
dc.contributor.author | Sheu, Gene | en_US |
dc.contributor.author | Chang, Ruey-Dar | en_US |
dc.contributor.author | Syu, Yi-Jhen | en_US |
dc.contributor.author | Liu, Chin-Ping | en_US |
dc.contributor.author | Chang, Hsiu-Fu | en_US |
dc.contributor.author | Wei, Zhao-Hui | en_US |
dc.date.accessioned | 2017-04-21T06:49:47Z | - |
dc.date.available | 2017-04-21T06:49:47Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4799-9928-6 | en_US |
dc.identifier.issn | 1946-1550 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136101 | - |
dc.description.abstract | This work investigates the degradation of electrical characteristics of amorphous silicon thin-film transistors during the accelerated ESD stress with a 40V high voltage and a high/low current of 2 mA/0.1 mu A conditions. Both the leakage current and the threshold voltage shift are severe as the accelerated ESD stress applied at the gate region. The 40V accelerated ESD stress with a high current has more severe impact on the electrical performance of device than that with a low current. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Reliability Analysis of Amorphous Silicon Thin-Film Transistors during Accelerated ESD Stress | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | PROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015) | en_US |
dc.citation.spage | 286 | en_US |
dc.citation.epage | 289 | en_US |
dc.contributor.department | 奈米中心 | zh_TW |
dc.contributor.department | Nano Facility Center | en_US |
dc.identifier.wosnumber | WOS:000380466200073 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |