Prioritization of Key In-Line Process Parameters for Electrical Characteristic Optimization of High-k Metal Gate Bulk FinFET Devices

Abstract

This work reports a novel method to discovery and optimize key fabrication in-line process of 16-nm HKMG bulk FinFET to improve device\'s performance and variability. The sensitivity analysis is utilized to prioritize key in-line process parameters which significantly boost device\'s performance and effectively reduce its variations. To extract hidden correlations among complex and a large number of in-line process parameters, data mining technique is applied to highlight and group associated in-line process parameters. The source of variations of in-line process parameters in each group is revealed and the optimized solution is proposed to reduce its sensitivity to devices\' fluctuation. Results show the dual gate-spacer, the source/drain (S/D) proximity, the S/D depth, and the S/D implant are grouped to the same cluster and significantly affect the threshold voltage (V-t,V-sat), the on-state current (I-d,I-sat) and the off-state current (I-d,I-off), but the key variation source of these parameters is the thickness of the dual gate-spacer. By replacing dual spacers with single spacers, the fluctuation of threshold voltage is 30% dropped.