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dc.contributor.authorHu, Yu-Chenen_US
dc.contributor.authorChang, Yao-Jenen_US
dc.contributor.authorWu, Chun-Shenen_US
dc.contributor.authorCheng, Yung Maoen_US
dc.contributor.authorChen, Wei Jenen_US
dc.contributor.authorChen, Kuan-Nengen_US
dc.date.accessioned2017-04-21T06:48:57Z-
dc.date.available2017-04-21T06:48:57Z-
dc.date.issued2014en_US
dc.identifier.isbn978-1-4799-7727-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/136338-
dc.description.abstractIn this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270 degrees C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn mu-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 mu m bump pitch, 40 mu m diameter of Cu/Sn mu-bump and 50 mu m diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.en_US
dc.language.isoen_USen_US
dc.titleResearch of Electroplating and Electroless Plating for Low Temperature Bonding in 3D Heterogeneous Integrationen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 9TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT)en_US
dc.citation.spage290en_US
dc.citation.epage293en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380572700066en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper