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dc.contributor.authorLu, Ting-Chouen_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorZan, Hsiao-Wenen_US
dc.date.accessioned2017-04-21T06:49:02Z-
dc.date.available2017-04-21T06:49:02Z-
dc.date.issued2016en_US
dc.identifier.isbn978-1-4673-9498-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/136386-
dc.description.abstractBeing operated with 0.3V supply voltage in a standard 65nm CMOS process, a new CMOS temperature compensated voltage reference circuit is proposed with subthreshold transistors and native nMOS. The reference drain current provided by the gate voltage of a subthreshold nMOS output transistor is nearly independent of temperature due to the existence of mutual compensation of mobility and threshold voltage variation. The new proposed temperature compensated voltage reference circuit functions well with the output voltage VREF of 168 mV at room temperature as no extra laser trimming is needed after fabrication. The total power consumption is about 70nW. With the VDD power supply of 0.3V, the temperature coefficient (TC) of voltage reference circuit is 105 ppm/degrees C as temperature varies from -20 degrees C to 100 degrees C. The chip size of the fabricated bandgap reference circuit is 0.0053mm(2).en_US
dc.language.isoen_USen_US
dc.subjectBandgap Reference Circuit (BGR)en_US
dc.subjectSubthreshold Regionen_US
dc.subjectNative nMOSen_US
dc.titleA 70nW, 0.3V Temperature Compensation Voltage Reference Consisting of Subthreshold MOSFETs in 65nm CMOS Technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2016 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department光電工程學系zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentDepartment of Photonicsen_US
dc.identifier.wosnumberWOS:000389516800051en_US
dc.citation.woscount0en_US
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