低電壓能帶隙參考電壓產生器之設計

Abstract

從理論分析，bandgap電路內的OPA，其performance對bandgap電路的整體效能有決定性的影響。再者，以nMOS作為輸入差動對的OPA，其Voltage Gain會比以pMOS作為輸入差動對的OPA要好。此外，bandgap電路內的OPA，若以pMOS作為輸入差動對，則其輸入端的voltage offset會被大幅放大。反之，以nMOS作為OPA輸入差動對的bandgap電路，其輸入端的voltage offset則只會被小幅放大。

然而，由於bandgap core circuit的電路架構限制，過去的bandgap電路，在使用CMOS製程的基礎下，均使用pMOS作為其OPA的輸入差動對。

因此本篇論文的研究方向，是藉由修改bandgap core circuit的架構，突破以往限制，設計出新式的bandgap電路，而其OPA是以nMOS作為輸入差動對。

最後，以nMOS作為輸入差動對的bandgap電路，與以pMOS作為輸入差動對的bandgap電路比較後發現：其layout所需面積較小，performance也較好。

本論文總共提出四種不同的電路架構。

Type A與Type B的設計、模擬是使用TSMC 0.18μm CMOS technology。其中Type A電路是使用pMOS作為運算放大器的輸入差動對; 而Type B電路則是使用nMOS作為其運算放大器的輸入差動對。實驗顯示，Type A與Type B 的輸出參考電壓可以達到772mV與737mV，相對應的最低工作電壓則為1.1V。

PSRR (power supply rejection ratio) 部份，Type A / B： -56 / -51 dB, -29 / -33 dB and -15.2 / -26 dB分別對應於1K, 10K, 100KHz。至於溫度補償方面，TC(eff) = 140 ppm/℃，from – 40℃ to 140℃。TC(eff)表現較差的原因是diffusion電阻與poly電阻在面對製程變化，其電阻值改變時，diffusion電阻值的改變率與poly電阻值的改變率並不相等，與電路架構無關, 這部份在第三章有詳細討論。

Type C與Type D則是將上述二個電路重新設計改良，使其能符合TT, SS, SF, FS, FF等5個 process corner condition。電路的設計、模擬是使用TSMC 0.35μm CMOS technology。其中Type C電路是使用pMOS作為運算放大器的輸入差動對; 而Type D電路則是使用nMOS作為其運算放大器的輸入差動對。實驗顯示，Type C與Type D的輸出參考電壓分別可以達到766mV與829mV，相對應的最低工作電壓則分別為1.3V與1.1V。PSRR部份，Type C / D： -18 / -25 dB, -2.7 / -10 dB and -0.1 / -0.42 dB分別對應於1K, 10K, 100KHz。PSRR的表現不如預期，推測是因為受到寄生電阻與寄生電容的影響。至於溫度補償方面，Type C / D: 90.2 / 34.1 ppm /℃ at Vdd = 1.3V. 由此實驗結果顯示：TC(eff) 表現回復正常，因為Type C / D bandgap core circuit內部，均使用相同的電阻材質(即擴散層片電阻)。

OP-Amplifier plays an important role in the bandgap circuits. According to the theory, the OPA which use nMOS as the input stage will get a better voltage gain than that using pMOS as the input stage. Besides, for OPA using pMOS as the input stage, the voltage offset on the input port will be multiplied largely. By contrast, for bandgap circuits that use nMOS as the OPA’s input stage, the voltage offset on the OPA’s input port will not be multiplied as largely as that with pMOS as the input stage.

However, because of the limitation of conventional bandgap circuit for providing the OPA’s input common mode voltage, most bandgap circuit was designed by using pMOS as the input stage in the past.

So we modify the conventional bandgap core circuit topology to create new type of bandgap circuit topologies. The new types of topologies can drive OPA that use nMOS as the input stage.

In this thesis, four kinds of low voltage-operated bandgap reference (BGR) circuits in CMOS technology, with high PSRR (power supply rejection ratio) are presented. Two of those proposed circuits use the OP-Amplifier in which the input stages are composed of pMOS. The others use nMOS as the input stage of the OP-Amplifier.

In this study, TSMC 0.18μm and 0.35μm CMOS process were adopted for circuit fabrication and verification. Type A and B were implemented by using 0.18μm process in which pMOS differential pair were adopted for type A while nMOS differential pair were employed for type B. Regarding type C and D which were fabricated by 0.35μm process, type C adopted pMOS differential pair while type D employed nMOS differential pair.

The experimental results show that it is possible to achieve 700mV reference voltage with low power supply voltage at 1.1V and a well-controlled temperature compensation performance.

For types A and B implemented by 0.18μm technology, the output reference voltages were achieved at 772mV and 737mV corresponding to the minimum supply voltage at 1.10V. PSRR under varying frequencies were achieved at -56 / -51 dB, -29 / -33 dB and -15.2 / -26 dB corresponding to 1K, 10K, and 100KHz for type A / B respectively. The effective temperature coefficient (TC(eff)) was as high as 140 ppm/℃ due to deviation of resistance ratio caused by the asymmetric process variation between diffusion resistors and poly-Si resistors.

As for type C and D fabricated by 0.35μm technology, the output reference voltages were achieved at 766mV and 829mV corresponding to the minimum supply voltage at 1.3 / 1.1V. PSRR under varying frequencies were achieved at -18 / -25 dB, -2.7 / -10 dB and -0.1 / -0.42 dB corresponding to 1K, 10K, and 100KHz for type C / D respectively. The PSRR is not as good as that predicted by simulation due to suspected parasitic resistance and capacitance effects. TC(eff) were achieved as 90.2 / 34.1 ppm/℃ for type C / D at Vdd = 1.3V, which shows significant improvement as compared with type A / B to adoption of diffusion resistors over the whole circuit chip.

Based on the simulation and measurement results, we make the conclusion that BGR circuits which use nMOS as the OP-Amplifier’s differential pair provide better performance and enable lower cost due to reduced chip area.