標題: Film-Profile-Engineered IGZO Thin-Film Transistors with Gate/Drain Offset for High Voltage Operation
作者: Wu, Ming-Hung
Lin, Horng-Chih
Li, Pei-Wen
Huang, Tiao-Yuan
電機學院
電子工程學系及電子研究所
College of Electrical and Computer Engineering
Department of Electronics Engineering and Institute of Electronics
公開日期: 2016
摘要: IGZO transistors with various gate/drain-offset lengths (L-GDO) were fabricated with the film-profile-engineering method. Breakdown voltage (V-BD) of the fabricated devices increases while transconductance (gm) decreases with increasing LGDO. In contrast, threshold voltage and subthreshold swing remain relatively unchanged. VBD of similar to 80 V is obtained with LGDO of 0.3 mu m . Output characteristics with operation voltage up to 50 V are also demonstrated, evidencing the capability of the device for high-voltage operation. Impact of hot-carrier stress is also investigated in this work.
URI: http://hdl.handle.net/11536/136412
ISBN: 978-1-4673-8258-8
ISSN: 1946-1550
期刊: Proceedings of the 2016 IEEE 23rd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
起始頁: 272
結束頁: 275
Appears in Collections:Conferences Paper