Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap

Abstract

Corner spacer design is investigated to improve the performance of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap compared with the all vacuum and all nitride spacer devices. All vacuum spacer devices with low permittivity reduce fringing capacitance and improve performance. However, for gate-to-source/drain underlap InGaAs-OI FinFET, all vacuum spacer device degrades source/drain resistance (Rsd) and ON current (Ion), thus exhibiting slight improvement in inverter delay compared with the all nitride spacer device. Corner spacer design comprising of high-k and low-k composite spacer is proposed to optimize Rsd and capacitance, and hence improve delay. Various lengths and heights of corner spacer for InGaAs-OI FinFET with different underlap length and fin height aspect ratio are investigated to optimized performance. The optimized corner spacer design is: (a) the length of corner spacer (Lcorner) is approximately equal to underlap length (Lun), and (b) the height of corner spacer (Hcorner) is proportional to the sum of fin height (Hfin) and gate oxide thickness (Tox). Compared with the all vacuum spacer InGaAs-OI FinFET with Lun = 6 nm, the optimized corner spacer design exhibits 36% and 10% improvements in Ion and inverter delay, respectively.