標題: Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices
作者: Hu, Vita Pi-Ho
Fan, Ming-Long
Su, Pin
Chuang, Ching-Te
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2013
摘要: Analysis of Germanium FinFET on SOI substrate (GeOI FinFET) at device and circuit level is presented. The amplified Band-To-Band Tunneling (BTBT) leakage of GeOI FinFETs is observed due to the parasitic bipolar effect, and the BTBT induced parasitic bipolar leakage dominates the leakage current of GeOI FinFET. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOI FinFET logic circuits and SRAMs. Drain-side underlap is the most effective way for leakage reduction of GeOI FinFETs, while increasing channel doping is the least effective way for leakage reduction of GeOI FinFETs. An optimum asymmetric underlap design in SRAM using asymmetric underlap pull-up and access transistors (PUAX-asym) is proposed. GeOI FinFETs with asymmetric underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.
URI: http://hdl.handle.net/11536/22855
ISBN: 978-1-4673-3082-4
ISSN: 1524-766X
期刊: 2013 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA)
顯示於類別:會議論文