完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee, Shih-Wei | en_US |
dc.contributor.author | Kuo, Shu-Chiao | en_US |
dc.contributor.author | Chen, Kuan-Neng | en_US |
dc.date.accessioned | 2017-04-21T06:49:25Z | - |
dc.date.available | 2017-04-21T06:49:25Z | - |
dc.date.issued | 2016 | en_US |
dc.identifier.isbn | 978-1-4673-9478-9 | en_US |
dc.identifier.issn | 1930-8868 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/136431 | - |
dc.description.abstract | A novel electrical test structure is proposed to inspect the stacking fault in 3D integration. This approach is one nondestructive analysis of the misalignment investigation. In order to determine the misalignment of wafer/chip stacking, the metal line pattern is designed to detect the direction and quantity of stacking fault. Testing circuit diagram is proposed and simulated for efficient measurement. In addition, different types of stacking fault including translation, rotation, and run out are discussed and formulated. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Electrical Testing Structure for Stacking Error Measurement in 3D Integration | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2016 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000389022000020 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |