標題: Low Temperature Copper-Copper Bonding of Non-Planarized Copper Pillar With Passivation
作者: Tsai, Yi-Chieh
Hu, Han-Wen
Chen, Kuan-Neng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Three-dimensional integration;Cu-Cu bonding;chip stacking
公開日期: 1-八月-2020
摘要: Low-thermal-budget (180 degrees C for 15 sec) Cu pillar to Cu pillar bonding with Pd passivation under the atmosphere is developed without any planarization pretreatment before the bonding process. The bonded structure is investigated with material analysis, electrical measurement and reliability test. The results show that although the Cu pillar has a high roughness surface due to the electroplating process with a high deposition rate, Cu atoms can still diffuse and connect through the passivation layer and perform the low-thermal-budget Cu pillar direct bonding. Low specific contact resistance and stable resistance of daisy chain shown in the reliability test reveal the excellent bonding quality and integrity. This Cu-Cu bonding method is therefore favorable for chip stacking technology development in 3D packaging domain.
URI: http://dx.doi.org/10.1109/LED.2020.3001163
http://hdl.handle.net/11536/155190
ISSN: 0741-3106
DOI: 10.1109/LED.2020.3001163
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 41
Issue: 8
起始頁: 1229
結束頁: 1232
顯示於類別:期刊論文