標題: High-gain, Low-voltage BEOL Logic Gate Inverter Built with Film Profile Engineered IGZO Transistors
作者: Lyu, Rong-Jhe
Chiu, Yun-Hsuan
Lin, Horng-Chih
Li, Pei-Wen
Huang, Tiao-Yuan
電機學院
電子工程學系及電子研究所
College of Electrical and Computer Engineering
Department of Electronics Engineering and Institute of Electronics
公開日期: 2016
摘要: We demonstrate InGaZnO (IGZO) TFTs with channel-length (L) tunable V-th for high-gain BEOL logic gate inverters in a unique filmprofile engineering (FPE) approach. In this FPE scheme the thickness and film profile of gate oxide and IGZO active layer are directly tailored by L (0.4 - 0.8 mu m) in a single step, leading to a wide-ranging tunability in V-th of -0.2 -+1.6V at no expense of additional masks and process steps. This provides an effective degree of freedom in the layout design for the realization of area-saving, high-gain unipolar logic inverters with load-transistors. Record-high voltage gain of 112 is demonstrated from the unipolar logic inverter with depletion-load 0.4 mu m IGZO TFT and 0.7 mu m IGZO drive-transistor, respectively, at operation voltage (V-DD) of 9V.
URI: http://hdl.handle.net/11536/136433
ISBN: 978-1-4673-9478-9
ISSN: 1930-8868
期刊: 2016 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA)
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