On-Chip ESD Protection Design for HV Integrated Circuits

Full metadata record

DC Field	Value	Language
dc.contributor.author	Ker, Ming-Dou	en_US
dc.date.accessioned	2017-04-21T06:48:17Z	-
dc.date.available	2017-04-21T06:48:17Z	-
dc.date.issued	2016	en_US
dc.identifier.isbn	978-1-4673-8969-3	en_US
dc.identifier.issn	2159-3523	en_US
dc.identifier.uri	http://hdl.handle.net/11536/136468	-
dc.description.abstract	Electrostatic discharge (ESD) protection has been an important reliability issue to CMOS integrated circuits, especially in high-voltage (HV) applications. In this invited talk, a brief overview on ESD protection designs for HV integrated circuits is presented. The useful and safe solutions are highlighted for real applications in HV IC products.	en_US
dc.language.iso	en_US	en_US
dc.subject	ESD protection	en_US
dc.subject	high-voltage (HI) IC	en_US
dc.title	On-Chip ESD Protection Design for HV Integrated Circuits	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	7TH IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC) 2016	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000386737900177	en_US
dc.citation.woscount	0	en_US
Appears in Collections:	Conferences Paper