Low-power low-voltage reference using peaking current mirror circuit

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Cheng, MH	en_US
dc.contributor.author	Wu, ZW	en_US
dc.date.accessioned	2014-12-08T15:19:09Z	-
dc.date.available	2014-12-08T15:19:09Z	-
dc.date.issued	2005-05-12	en_US
dc.identifier.issn	0013-5194	en_US
dc.identifier.uri	http://dx.doi.org/10.1049/el:20050316	en_US
dc.identifier.uri	http://hdl.handle.net/11536/13722	-
dc.description.abstract	A low-power low-voltage bandgap reference using the peaking current mirror circuit with MOSFETs operated in the subthreshold region is presented. A demonstrative chip was fabricated in 0.35 mu m CMOS technology, achieving the minimum supply voltage 1.4 V, the reference voltage around 580 mV, the temperature coefficient 62 ppm/degrees C, the supplied current 2.3 mu A, and the power supply noise rejection ratio of -84 dB at 1 kHz.	en_US
dc.language.iso	en_US	en_US
dc.title	Low-power low-voltage reference using peaking current mirror circuit	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1049/el:20050316	en_US
dc.identifier.journal	ELECTRONICS LETTERS	en_US
dc.citation.volume	41	en_US
dc.citation.issue	10	en_US
dc.citation.spage	572	en_US
dc.citation.epage	573	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:000229769900003	-
dc.citation.woscount	13	-
顯示於類別：	期刊論文

文件中的檔案：

若為 zip 檔案，請下載檔案解壓縮後，用瀏覽器開啟資料夾中的 index.html 瀏覽全文。