一種帶通採樣且降低抖動量的新式架構接收器

Abstract

在這篇論文中，我們研究了帶通取樣OFDM 接收器的性能並且提出了一種新式低成本方式去消除採樣不準確性所帶來的影響。對於提出的系統架構，訊號的分析以及模擬結果都描述在這篇論文內，經由結果我們可以觀察到我們提出的系統可以消除採樣不準確性所帶來的影響。此外，我們設計了一些硬體設施來實現此系統。我們針對採樣射頻訊號做了一塊類比數位轉換器的印刷電路板，而提出的系統則是設計在一塊低成本的FPGA晶片裡面，此系統的工作頻率為140MHz。我們也設計了一套軟體介面不只可以展示出量測結果，也可以完成後段演算法所需的數學運算。

In this thesis, we investigate the performance of a band-pass sampling OFDM receiver and propose a new low-cost approach to mitigate the effect of sampling uncertainty. Signal analysis and simulation results are provided for the proposed system. The observed measurements show that the proposed system can reduce the effect of sampling uncertainty. Additionally, the proposed system has been implemented in hardware. The ADC PCB board is for sampling RF signal, and the proposed algorithm is designed in a low-cost FPGA chip which uses a clock rate of 140MHz. We also design a software programme for measurement with LabVIEW. The software programme can not only show the result but also do mathematical operations for the posterior segment of proposed algorithm.