Title: 三維積體電路晶片間接點之研究: Cu3Sn接點與金對金直接接合
Study of vertical interconnects of 3D IC: Cu3Sn joints and Au-to-Au direct bonding
Authors: 邱韋嵐
陳智
Chiu, Wei-Lan
Chen, Chih
材料科學與工程學系所
Keywords: 三維積體電路;Cu3Sn;直接接合;通道;介金屬化合物接點;金對金;3DIC;Cu3Sn;direct bonding;channel;IMC joint;Au-to-Au
Issue Date: 2015
Abstract: 近年來隨著科技的演進,更多功能的電子產品大量問世。「多功能」意味著單一電子元件在單位面積內需要放入更多的電晶體,於封裝而言,則意味著更小的線寬、線距以及封裝尺寸。傳統的二維封裝在提昇密度上有其極限,因此三維積體電路封裝近來蔚為主流。三維積體電路封裝可以堆疊多顆晶片,進行三維空間垂直整合,不僅提高封裝密度,達到封裝體積縮小的目的,同時也能改善耗能與產熱等問題。本論文主要是針對三維積體電路封裝技術發展,以研究微凸塊為主軸,研究不同材料於接點的應用以及其特性的探討。第一部分主要研究介金屬化合物作為接點的適用性。在文獻上Cu3Sn介金屬比銲錫有更好的斷裂韌性,為了提升機械性質,我們在微凸塊上製作以Cu3Sn為主的介金屬化合物接點,並且應用奈米雙晶銅作為金屬墊層 。在奈米雙晶銅墊上電鍍出0.44 μm、1 μm、10 μm的純錫,然後分別在260 oC與340 oC下迴銲形成Cu3Sn接點。發現在Cu3Sn層裡幾乎沒有Kirkendall孔洞產生,並用介金屬的成長動力學分析來預測形成Cu3Sn接點所需的時間與銲錫厚度。第二部分著重於觀察高銲錫Cu/Sn/Cu在260 oC與340 oC的冶金反應,在介金屬層中發現有通道的存在,此一通道生成會加速原子間的擴散而影響介金屬的成長動力學。 第三部分主要探討使用其他材料作為接點的可行性,若除去銲錫直接使用金對金的直接接合,將可避免異質材料接合的可靠度議題。在這主題中,我們使用直流電製作垂直於基板的奈米雙晶金,使用脈衝電流製作平行於基板的奈米雙晶金薄膜,並觀察其金的晶體結構,晶粒方向性,硬度與熱穩定性。接著在溫度為200 oC下壓力為0.76 MPa且在10-3 torr的低真空環境下熱壓15分鐘完成接合,其接合狀況良好,且接合溫度比銲錫回銲溫度還要更低。研究顯示金對金直接接合可以作為製作微凸塊的技術選項,同時,因為金具抗氧化性可以在大氣環境下接合,並且具有許多優異的機械性質可以增加電子元件的可靠度,對三維積體電路封裝也是一種很好的選擇。
With evolution of technology, more multi-function chips have be integrated into electronic devices. The “multi-function” means more transistors being placed onto the unit area of each electric component. In the aspect of electronic packaging, it makes smaller line pitch, width and package size become more important. Due to the limitation of miniaturization of two-dimensional packaging, three-dimensional integrated circuits gets more attention in recent years. With three-dimensional packaging technique, many different chips could be stacked on each other. It not only increases packaging density to reduce the packaging size, but also improves the problems of energy consumption and heat production. This study mainly focuses on technique of fabricating 3D-IC, especially for microbumps. Researches about applications and properties of different joints are introduced. The first part of this study is about applicability of intermetallic compound joints. Some literatures have shown Cu3Sn has better mechanical properties, such as fracture toughness and hardness. To improve mechanical properties of joints, full Cu3Sn joints were fabricated with electroplated nanotwinned Cu as under bump metallurgy. 0.44 μm, 1 μm and 10 μm-thick tin layers were electroplated on nanotwinned Cu, and then reflowed at 260 oC and 340 oC respectively to form full Cu3Sn joints. Kirkendall voids barely existed by using nt-Cu. Furthermore, we make kinetics analysis to predict the time needed for Sn and Cu to form full Cu3Sn joints at 260 oC. The second part of this study describes metallurgical reaction in Cu/Sn/Cu sandwich structure containing thicker tin layer. The sandwiches were reflowed at 260 oC and 340 oC. In this part, some channels were observed between Cu3Sn and Cu6Sn5 layer. These channels act as a fast diffusion path and would affect the kinetics about growth of intermetallic compounds in microbumps. The third part is mainly about surveying other materials to replace solders in micro-joints. Regarding to the reliability concerns arised by heterogeneous material joints, we bonded Au film with Au film. In this part, we electroplated nanotwinned Au film with twinning planes being parallel to substrates by pulse current and being normal to substrates by direct current. The grain structure and orientation as well as film hardness and thermal reliability were investigated. For bonding process, thermal compression of 0.76 MPa was applied at 200 oC for 15 mins in 10-3 torr vacuum. The result shows Au-Au bonding can be achieved at the temperature lower than reflowing temperature of soldering. It also shows that Au-Au direct bonding could be a promising candidate for microbumps. In addition, gold could be bonded in the atmosphere due to its antioxidant property, and it has many excellent mechanical properties that can increase the reliability of electronic packaging. The outcome demonstrates that gold would be a good choice for three-dimensional integrated circuit packaging.
URI: http://etd.lib.nctu.edu.tw/cdrfb3/record/nctu/#GT070081516
http://hdl.handle.net/11536/138529
Appears in Collections:Thesis