薄膜輪廓工法之非晶銦鎵鋅氧薄膜電晶體之研製與分析

Abstract

本篇論文中，我們借由薄膜輪廓工法，成功製作並分析高效能次微米通道長度之非晶銦鎵鋅氧薄膜電晶體。此工法中，搭配著合適的薄膜沉積技術，僅需一道光罩即可製作薄膜電晶體。而且使用氧化鋁 (Al2O3) 以及二氧化矽 (SiO2) 當作閘極氧化層之元件，展現出很好的特性，例如高的場效遷移率 (Field-effect mobility) (17~20 cm2/V·s)、陡峭的次臨界擺幅 (Subthreshold swing) (60~80 mV/dec)，以及大的開關電流比 (ION/IOFF) (~109)。 我們研究了許多製程上的參數對於元件電性上的影響。在銦鎵鋅氧沉積時的氧流量對次臨界擺幅和臨界電壓 (Threshold voltage) 的影響十分劇烈；反之在氮氣環境下的退火能有效地改善元件穩定性。發生在通道層和源汲極 (Source/drain) 電極間的界面反應，對於元件特性的提升起了重要的作用。在銦鎵鋅氧表面之源汲極處做氬氣電漿處理後，能進一步改善元件的開電流 (ON current)。這是因為有效地降低了源汲極的接觸電阻。在銦鎵鋅氧薄膜電晶體上使用有機鈍化層能展現出良好的電性，和使用電漿增強化學氣相沉積 (PECVD) 的SiO2及氮化矽(SiN) 鈍化層的元件相比，在通道背面缺少了由氫引起之摻雜效應造成的。 我們利用薄膜輪廓工法加上光阻削減技術，進一步將元件的通道長度縮減到小於100奈米。和先前已報導過的數據相比，我們所製作的元件展現出極佳的特性。我們的分析進一步指出，對於極小尺寸的元件而言，源汲極串連電阻是不可避免且迫切需要解決的問題。 為了解決非自我對準薄膜輪廓工法所帶來的問題，我們提出了一個簡單的做法，得以製作出可自我對準的閘極銦鎵鋅氧薄膜電晶體。由於大幅減少了閘極和源汲極間的重疊面積，此元件在關閉狀態下的漏電流，和非自我對準的元件相比，降低了一個數量級，也由於減少了閘極和源汲極間的寄生電容，有著極佳的潛力可以提升電路特性。 最後，我們利用電腦輔助設計技術(TCAD)模擬，對傳統逆交錯型(Inverted-staggered)薄膜電晶體在不同通道厚度下(10~50奈米)之特性變化做了研究。分析指出，較厚的通道能降低狀態密度 (Density of states)以及得到較高的載子濃度(ND)，因此通道層較厚之元件展現出較好的特性。此外，我們借由模擬也研究了薄膜輪廓工法對元件特性改善之原因，結果指出，當通道載子濃度大於5 × 1017 cm-3時，它能降低元件源汲極處之展阻 (Spreading resistance)，再加上於源汲極處較厚通道層之狀態密度較低，因而能提升元件特性。

In this dissertation, we have successfully fabricated and characterized high-performance amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with sub-micron channel length by using the novel “film-profile-engineering” (FPE) approach. In this approach in conjunction with proper deposition techniques, only one mask is needed for the TFT fabrication. Devices with Al2O3 or SiO2 gate insulator reveal decent performance, such as high field-effect mobility (17~20 cm2/V·s), steep subthreshold swing (SS) (60~80 mV/dec) and large ON/OFF current ratio (~109). The effects of various process parameters on the device’s electrical characteristics are also studied. Oxygen flow rate during the IGZO sputtering is found to affect SS and threshold voltage significantly, while the annealing conducted in a nitrogen environment can improve device’s stability. Interfacial interactions taking place at the interface between channel and S/D electrodes play an important role in the enhancement of device performance. Ar plasma treatment on the IGZO in the S/D regions can further improve the ON current due to the reduction in the S/D contact resistance. IGZO TFTs with organic passivation layer exhibit good electrical characteristics due to the lack of hydrogen-induced doping effect on the back side of channel as compared with the inorganic SiO2 and SiNX passivation layers deposited by plasma-enhanced chemical vapor deposition. We have further shrunk the channel length of the FPE devices down to sub-100 nm by incorporating photoresist trimming technique in the fabrication. The fabricated devices exhibit excellent characteristics as compared with the previously reported data. Our investigation also revealed that S/D series resistance is an inevitable issue to be solved for the ultra-short devices. To address the issues raised by the non-self-aligned FPE scheme, we proposed and demonstrated a simple method to obtain self-aligned bottom-gate FPE IGZO TFTs. It shows a significant reduction in OFF-state current thanks to a small gate-to-S/D overlap length (LOV), showing a great potential to boost circuit performance by reducing parasitic gate-to-S/D capacitances. Finally, we used TCAD simulation to investigate the thickness-dependent performance of inverted-staggered IGZO TFTs with channel thickness ranging from 10 to 50 nm. The analysis indicates that the reduced density-of-states as well as the higher carrier concentration (ND) in the thicker channel layer account for the better performance as observed from devices with a thicker channel. Furthermore, the performance improvement by the FPE configuration is also investigated via simulation, and the results indicate that FPE structure is beneficial for the oxide TFTs due to the smaller spreading resistance and lower DOS at the S/D regions as the ND > 5 × 1017 cm-3