電阻式記憶體及SONOS快閃式記憶體中介電層缺陷造成之可靠度效應研究

Abstract

本論文主要探討電阻式記憶體(RRAM)以及SONOS快閃式記憶體之各種由介電層缺陷造成之可靠度效應。其中包含RRAM中設定干擾錯誤時間(SET-disturb failure time)、隨機電報雜訊(RTN)以及SONOS中單電子造成臨界電壓(Vt)維持流失之統計量測。蒙地卡羅及統計數值模型亦在此論文中建立以驗證相關理論及實驗結果。

第一章首先介紹近年來非揮發性記憶體之演進發展以及遇到之各種主要可靠度議題。另外在目前在RRAM交叉式陣列(crossbar array)中會遇到之可靠度議題也將在此章節說明。吾人亦會指出單電子現象在SONOS快閃式記憶體中之影響。最後，此論文之整體架構將在此章節中介紹。

第二章中，吾人發現在鎢介電質RRAM中一種寫入干擾失敗時間(write-disturb failure time)新的衰退機制，且此機制與設定(SET)/重設(RESET)操作循環有關。高阻態元件在某一特定次數之設定/重設操作循環時，寫入干擾時間會突然大幅下降數個量級數。雖然記憶體視窗仍然保持，但卻可觀測到偶發性之過度重設。為了進一步研究此衰退現象，吾人在高阻態下利用定電壓施壓並量測施壓造成漏電流及低頻雜訊以觀測缺陷在RRAM介電質中生成情形。定電壓施壓可仿真出設定/重設操作循環時高電壓施壓造成缺陷生成現象。吾人發現在高阻態斷開區中，不論是在定電壓施壓或設定/重設操作循環施壓，低電場下之缺陷幫助穿隧現象將逐漸增強。而高電場施壓產生之缺陷與設定產生之氧空缺不同，無法被重設操作抹除，且此種缺陷將會造成重設耐受性失效。吾人建立了三維穿隧效應機制之蒙地卡羅模型以模擬設定干擾失敗時間。此模擬同時包含高電場施壓生成之缺陷及設定干擾所產成之氧空缺，亦成功解釋此種突發式設定干擾時間大幅下降現象是由於高電場施壓缺陷產生導通路徑所造成。

另外兩種會影響設定干擾失敗時間之機制，即電阻視窗和設定干擾電壓，將在第三章中提出。吾人發現低阻態之電流準位將強烈影響設定干擾失敗時間，且此現象是由於設定干擾失敗時間之Weibull斜率很小所造成。此外，吾人利用統計量測方式探討設定干擾電壓與設定干擾時間之關係。

在第四章，吾人在鉿介電質RRAM中對二階RTN振幅分布做了統計量測。與低阻態相比，RTN振幅統計分布在高阻態時有一大振幅tail。吾人在各種讀取偏壓下量測電子捕捉時間與釋放時間，並萃取RTN缺陷在鉿介電質中之位置，發現缺陷位置與RTN振幅大小有關。由於在重設操作後，氧空缺在斷開區並非均勻分布，故可推估高阻態下之大振福RTN tail為靠近陰極電擊所造成。

第五章探討在SONOS中臨界電壓維持分布tail效應。吾人在NOR型態多階(multi-level)SONOS量測單電荷流失所造成之臨界電壓變化。實驗結果顯示: (1) 單電荷流失造成之臨界電壓變化呈現一指數分布，且歸因於隨機寫入電荷形成之電流穿隧效應。(2) 在多階SONOS中，此指數分布之標準差會隨著寫入電荷數量或寫入臨界電壓等級上升而上升。此外，吾人量測一512Mb數次寫入SONOS元件之臨界電壓維持分布，並發現此分布有一明顯tail。一包含穿隧效應及Poisson分布之多電荷流失數值模型亦在此章節中被建立。此模型可成功模擬出512Mb SONOS中所觀測到之tail現象，且此tail效應可用電子穿隧效應解釋。

最後，第六章為本論文之結論及未來預計之研究方向。

This dissertation will focus on major reliability issues in random access memory (RRAM) and SONOS flash memory induced by traps in a dielectric. Statistical characterization of SET-disturb failure time in an RRAM crossbar array, random telegraph noise (RTN) and single program charge induced Vt retention loss in SONOS are performed. Monte-Carlo simulation model and numerical simulation model are also developed to corroborate our characterization results.

In Chapter 1, first, the evolution of the nonvolatile memory technology in recent years and the major reliability concerns are addressed. Second, the applications and the reliability issues of an RRAM crossbar array will be demonstrated. Also, the impact of single charge phenomenon in SONOS flash memory will be pointed out. The organization of this dissertation will be given in this chapter.

In Chapter 2, a new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. To investigate this new degradation mode, we perform constant voltage stress in HRS to characterize trap generation in a switching dielectric by measuring a stress-induced leakage current and low-frequency noise. The constant voltage stress is to emulate high-field stress and thus trap creation in SET/RESET cycling. We find that a low-field current in HRS via trap-assisted tunneling in a rupture region increases gradually in both constant voltage stress and SET/RESET cycling stress. The high-field stress-generated traps, unlike SET-induced oxygen vacancies, cannot be annihilated by RESET operation and are held responsible for a RESET endurance failure. A three dimensional Monte Carlo model based on a percolation concept of oxide breakdown is developed to simulate a SET-disturb failure time. Our model includes both stress-generated traps and SET-disturb induced oxygen vacancies. The model can well explain observed abrupt and drastic SET-disturb lifetime degradation, which is attributed to the formation of a conductive percolation path of stress-generated traps.

In Chapter 3, two more factors affecting SET-disturb failure time (f) including resistance window in operation and SET-disturb voltage are investigated. The dependence of f on resistance window in operation is characterized. We find that f is greatly affected by the current level of LRS. The strong LRS dependence of f is attributed to a small Weibull slope of f. In addition, we perform statistical characterizations of f at different SET-disturb voltages. A relationship between f and a SET-disturb voltage in a stressed cell is given.

Statistical characterization of two-level random telegraph noise (RTN) amplitude distribution in a hafnium oxide resistive memory has been performed in Chapter 4. We find that two-level RTN in HRS exhibits a large amplitude distribution tail, as compared to LRS. To investigate an RTN trap position in a hafnium oxide film, we measure the dependence of electron capture and emission times of RTN on applied read voltage. A correlation between an RTN trap position and RTN amplitude is found. Owing to a non-uniform distribution of oxygen vacancy after a RESET process, RTN traps near the cathode are responsible for an RTN large-amplitude tail in HRS mostly.

In Chapter 5, a Vt retention distribution tail in a Multi-Time-Program (MTP) SONOS memory is investigated. We characterize a single program charge loss induced Vt in NOR-type multi-level SONOS cells (MLC). Our measurement shows that (i) a single charge loss induced Vt exhibits an exponential distribution in magnitudes, which is attributed to a random program charge induced current path percolation effect and (ii) the standard deviation of the exponential distribution depends on a program charge density and increases with a program Vt level in a MLC SONOS. In addition, we measure a Vt retention distribution in a 512Mb MTP SONOS memory and observe a significant Vt retention tail. A numerical Vt retention distribution model including the percolation effect and a Poisson distribution based multiple charge loss model is developed. Our model agrees with the measured Vt retention distribution in a 512Mb SONOS well. The observed Vt tail is realized mainly due to the percolation effect.

Finally, conclusions are made and future work is described in Chapter 6.