使用氧化鑭和二氧化鉿複合氧化層結構之砷化銦鎵金氧半導體電容器研究

Abstract

在本篇論文中，我們探討二氧化鉿(HfO2)與氧化鑭(La2O3)沉積在砷化銦鎵(In0.53Ga0.47As)表面所形成的金屬-氧化物-半導體(MOS)元件之應用。二氧化鉿和砷化銦鎵界面品質可藉由中間插入一層很薄的氧化鑭層而改善。本實驗透過分子束沉積方法將同樣總高度的高介電係數氧化層結構沉積在砷化銦鎵表面以製得金-氧-半導體電容器；此三種高介電材質分別為單獨之二氧化鉿，二氧化鉿/氧化鑭和氧化鑭/二氧化鉿疊層結構。我們可以從X-射線光電子能譜儀(XPS)，穿透式電子顯微鏡(TEM)和電容量-電壓(C-V)量測方法分析氧化層和半導體間的介面品質。藉此金氧半元件電容-電壓關係以及介面雜質缺陷可得到比較，以調查插入氧化鑭薄層對二氧化鉿/砷化銦鎵金-氧-半導體電容的影響。氧化層厚度與沉積後熱退火溫度對複合性氧化層之金-氧-半導體電容介面性質表現也在此論文中被探討。此外，交錯層疊的0.8奈米二氧化鉿/0.8奈米氧化鑭以及0.8奈米氧化鑭/0.8奈米二氧化鉿也分別沉積在砷化銦鎵表面。 實驗結果顯示，複合氧化層結構系統表現較單一氧化層系統為佳；氧化鑭/二氧化鉿系統亦較二氧化鉿/氧化鑭系統為佳。此外，0.5奈米氧化鑭/0.5奈米二氧化鉿亦較0.8奈米氧化鑭/0.8奈米二氧化鉿厚度結構為佳。 6奈米二氧化鉿/0.8奈米氧化鑭結構砷化銦鎵金-氧-半導體電容器最終得到極佳的電容-電壓特性與低達2×1011 cm-2.eV-1的介面雜質缺陷密度。另一方面伴隨著熱退火溫度和疊層厚度最適化，使用三層複合氧化層亦得到在一千赫茲頻率時低達1.41奈米的電容等效厚度；多層之0.8奈米氧化鑭/0.8奈米二氧化鉿結構砷化銦鎵金-氧-半導體電容亦達到2.8%頻率散度與7.0 x 1011cm-2.eV-1介面雜質缺陷密度。 最後，使用六層的0.5奈米氧化鑭/0.5奈米二氧化鉿複合氧化層砷化銦鎵結構，金-氧-半導體電容器達到1奈米等效氧化層厚度，88×10-3伏特磁滯現象的電壓變化量以及1.9×1012 cm-2.eV-1介面雜質缺陷密度。

In this dissertation, HfO2 and La2O3 deposited on n-In0.53Ga0.47As for metal-oxide-semiconductor (MOS) device application were studied. The interface between HfO2 and n-In0.53Ga0.47As was improved by inserting a thin La2O3 layer. Three different kinds of high-k oxide structures: HfO2, HfO2/La2O3 and La2O3/HfO2 of same total thickness were deposited by molecular beam deposition on n-In0.53Ga0.47As to fabricate MOS capacitors. XPS, TEM and C-V measurements were used for the interface analysis between oxide and semiconductor. With these, the MOS devices capacitance-voltage and interface traps density were compared to investigate the influence of the thin La2O3 insertion layer on the HfO2/In0.53Ga0.47As MOS capacitor. The effects of oxide thickness and post-deposition annealing (PDA) temperature on the interface properties of the composite oxide MOS capacitors were also studied. In addition, interleaved HfO2 (0.8 nm)/La2O3 (0.8 nm) and La2O3 (0.8 nm)/HfO2 (0.8 nm) multilayers were deposited on n-In0.53Ga0.47As. Experiment results revealed that the binary oxide structural system performance is better than single oxide system and the La2O3/HfO2 structure is better than the HfO2/La2O3 structure. Moreover it was found La2O3 (0.5nm)/HfO2 (0.5nm) multilayer structure performs better than La2O3 (0.8 nm)/HfO2 (0.8 nm). Eventually, excellent capacitance-voltage characteristics and low interface traps density of 2×1011 cm-2.eV-1 were achieved by the HfO2(6nm)/La2O3(0.5nm) on n-In0.53Ga0.47As MOS capacitor. On the other hand, it was found that a low CET of 1.41nm at 1 kHz was achieved using three-layer composite oxides; a small frequency dispersion of 2.8% and an excellent Dit of 7.0 x 1011cm-2.eV-1 can be achieved using multiple layers of La2O3 (0.8 nm) and HfO2 (0.8 nm) on the n-In0.53Ga0.47As MOS capacitor with optimum thermal treatment and layer thickness. Finally, a 1 nm equivalent-oxide-thickness dielectric with small hysteresis of 88mV and Dit of 1.9×1012 cm-2.eV-1 was achieved for a 6 layers of La2O3 (0.5nm)/HfO2 (0.5nm) composite oxide structure on In0.53Ga0.47As MOS capacitor with PDA temperature of 450C.