具背向閘極之混合式P/N通道無接面場效電晶體之研究

Abstract

此篇論文延續我們團隊開發之混合式P/N通道無接面電晶體，在此結構下再加入一背向閘極，成為具背向閘極之混合式P/N通道無接面場效電晶體，利用混合式P/N通道中N型基板產生空乏區，使等效通道厚度變薄，實際元件通道厚度將不再侷限於10奈米，以此降低通道製程之困難度，並藉由調變背向閘極之偏壓來增進閘極控制能力提升元件電特性。 本篇論文首次開發製成具背向閘極之混合式P/N通道結構多晶矽無接面場效電晶體。此新穎的結構可藉由調變背向閘極偏壓8伏特至-8伏特展現極佳的電特性，像是陡峭之次臨界擺幅(subthreshold swing, SS) 69 mV/dec、幾乎沒有之汲極引致能障下降(drain-induced barrier lowering, DIBL)值為6mV/V、較高的開關電流比(Ion/Ioff ratio >108)、好的臨界電壓(threshold voltage, Vth)調變能力、較低的低頻雜訊。開電流上升同時關電流下降伴隨增加的背向閘極負偏壓，這個特性突破了傳統具背向閘極結構元件之開關電流趨勢。增強的開關電流比值在25℃至125℃時仍能維持，因此具背向閘極之混合式P/N通道結構之多晶矽無接面場效電晶體在低功耗、系統級晶圓及系統級封裝之應用有極佳的潛在優勢。 此外，此篇論文亦首次做出垂直堆疊多層混合式P/N通道無接面場效電晶體，詳細說明製程及結構外，基本電性也將在內文提及與討論。特別的是，開關電流比可以大於109，多層混合式P/N通道無接面場效電晶體如此良好的電性與簡易的製程在3維堆疊積體電路應用上有極高的發展希望。

In this work, we introduce a double-gated junctionless (JL) field-effect transistor (FET) which contains a hybrid P/N channel proposed by our team previously. The hybrid P/N channel is composed of a p+ channel stacked on an n+ Si layer. The naturally formed depletion layer between the two layers may reduce the effective thickness of the P-type channel. This scheme may not only relieve the constraint imposing on the channel thickness of a JL device, but also reducing the process complexity. Furthermore, the device performance may benefit from the negative bias applied to the back-gate. The above scheme was demonstrated, for the first time, with a polycrystalline silicon-based technology. The fabricated devices show excellent electrical characteristics in terms of steep subthreshold swing (SS = 69 mV/dec), negligible drain-induced barrier lowering (DIBL = 6mV/V), high On-Off current ratio (Ion/Ioff > 108), good threshold voltage (Vth) modulation capability (= 0.08) and reduced low-frequency noise (LFN). Ion increases while Ioff decreases simultaneously as a more negative Vbg is applied. The enhancement of Ion/Ioff ratio is maintained as the temperature is increased from 25℃ to 125℃. The feature makes the scheme potential for low power, System-on-Chip (SoC) and System-on-Panel (SoP) applications. This thesis also demonstrated a JL device with vertically stacked multi-hybrid P/N channels. The fabrication process flow is discussed in detail and the basic electrical characteristics are presented. Specifically, the Ion/Ioff of multi-hybrid P/N channel JL-FET is more than 109. The good device characteristics along with the simple fabrication enable this approach promising for future 3D stacked integrated circuits applications.