氧化矽與氧化鈦複合材料的電阻式記憶體電性切換特性探討

Abstract

隨著科技日益發展，非揮發性記憶體在日常生活中扮演一個很重要的角色，例如：行動電話、數位相機、可攜帶式裝置。其中快閃記憶體被視為目前主流，根據ITRS可知，快閃記憶體的穿隧氧化層是否能繼續微縮是目前技術的關鍵，隨著厚度變薄(小於10奈米)載子容易流失，這會導致控制不易或資料讀取錯誤。為了解決這個問題，目前有許多新世代的記憶體出現，例如相變化隨機存取、鐵電隨機存取記憶體、磁性隨機存取記憶體和電阻式隨機存取記憶體，其中電阻式記憶體具有發展潛力，它具有低操作電壓、高操作速度、低功耗、高度整合和簡單結構等等。 此篇論文的研究，我們報告指出在鎳／二氧化鈦／氮化鉭單層電阻式記憶體中加入二氧化矽當作介面層比純粹單層結構的鎳／二氧化鈦／氮化鉭及鎳／二氧化矽／氮化鉭特性上會有顯著的提升。本篇論文中，我們實現了四級的電阻式記憶體，其一、二、三、四級對應到67、117、140、105的開關電阻比，分別有著0.52毫瓦、1.975毫瓦、3毫瓦、18.9毫瓦的設定功率以及0.156微瓦、1.02微瓦、4.8微瓦、58.5微瓦的重設功率。此元件還展現出了好的耐受力(100個週期) 及夠長的資料保存時間(溫度85度下2000秒) ，除此之外，二氧化矽的加入作為介面層提供了更好的均勻度。

The field of computing is facing gradual changes from just computing, towards “memorizing” and “searching” and this requires huge amounts of data storage. NAND Flash has been the key driver of non-volatile memory supplying all such demands. However, the charge storage based operation principle and adoption of a semiconductor channel impose certain limitations in pushing its design rule down to ≈5 nm, even with the Vertical NAND (V-NAND) configuration. Simultaneously, it is also necessary to bridge the speed gap between DRAM and NAND Flash, which calls for alternate memory devices such as ReRAM, MRAM, FRAM, PRAM, STT-RAM, and CB-RAM.

Resistance switching Random Access Memory (ReRAM) has been extensively studied for the past 1.5 decades since the renewed interest in this memory was triggered by IBM Zürich group in 2000 with a hope that the ReRAM can replace or succeed multilevel-cell (MLC) NAND flash memory when it’s scaling ends. ReRAM offers fast read/write speeds, low power operation , simple fabrication processes, good endurance and retention characteristics and multi-level capabilities which can scale down the cost per bit. However, certain challenges such as lack of intra-cell uniformity, high forming voltages and low yield supported by poor endurance and retention characteristics hinder its commercial success. Despite extensive research in this field during past decades, one single ReRAM material that can meet all these requirements has not emerged to date.

In this study, it has been depicted that by using SiO2 as a buffer layer in the Ni/TiO2/TaN RRAM structure, the device characteristics can be significantly improved when compared to single layer devices such as Ni/TiO2/TaN and Ni/SiOx/TaN. Multi-level resistance states have been realized with resistance windows of 67,117,140 and 105 along with SET powers of 0.52 mW, 1.975 mW, 3 mW, 18.9 mW and RESET powers of 0.156 µW, 1.02 µW, 4.8 µW and 58.5 µW for Levels 1, 2, 3 and 4. Alternatively, good endurance characteristics up to 100 switching cycles and retention for up to 2000 seconds at 85 ºC has been demonstrated. Additionally, a thin SiOx buffer layer also renders better uniformity to the otherwise, TiOx only device both, between devices and between runs.