具感測耦合效應之時序分析中更嚴格時間界限的逼近方法研究

Abstract

在積體電路設計裡，由於製程進步的影響，對於時序分析來說， 串音(crosstalk) 效應已經變成了一個很重要的議題。雖然有很多關 於考慮耦合效應的靜態時序分析(static timing analysis) 的研究已經被提出，但是電路的時間界限(timing bound) 可能還是太悲觀，而這是因為沒有考慮到錯誤耦合(false coupling) 以及對於特定路徑精煉(path refinement) 的影響。因此，在這篇研究裡，我們提出了一個架構，藉由功能時序分析(functional timing analysis) 的幫助下可以明確的考慮重要的串音效應，避免計算到因為錯誤耦合而造成的影響並進一步執行路徑精煉來接近真實的時間延遲並且得到一個比較嚴格 的時間界限。實驗結果顯示，在考慮串音效應的延遲下，利用所提供 的架構可以在ISCAS’85 以及ISPD2012 的電路上得到一個比較嚴格的 時間界限(特別是b19 有34.6% 的縮減)。而且，藉由事先設定一個下 限，整體的執行時間可以進步35%。

Crosstalk effect has become a critical issue for timing analysis in CMOS designs due to continuous technology scaling. Although several works about coupling-aware static timing analysis has been proposed, the timing bound may still be pessimistic due to false coupling and neglect of path refinement. Therefore, in this work, we proposed an framework that can explicitly consider the critical crosstalk effect, avoid estimating the unnecessary or false coupling based on functional timing analysis and further perform path refinement to approach toward the true delay and obtain tighter bounds. Experimental results show that using the framework can provide a tighter bound on crosstalk delay for several ISCAS’85 and ISPD2012 benchmark circuits. (in particular, by 34.6% for b19). Moreover, the runtime can be further improved by 35% after setting a lower bound.