多重邊界案例之功能時序分析

Abstract

在多重邊界案例(multi-corner) 下的時序分析(timing analysis) 在現今的超大型積體電路設計中越來越重要，為了能夠達到更好的時序收斂(timing closure)，必須要考慮製程變異(process variation) 所造成的電路時序變異(timing variation)，多重邊界案例下的靜態時序分析(multi-corner static timing analysis) 被提出來解決此問題，然而其忽略了電路中可能存在的錯誤路徑，造成了所估算出來的電路整體的延遲時間過於悲觀。因此，我們提出了一個多重邊界案例功能時序分析引擎(MCFTA Engine)，其能考慮電路中的錯誤路徑，能夠計算出較靜態時序分析更為精準的電路延遲時間。然而，隨著製程參數(process parameter) 的數量增加，MCFTA 的執行時間膨脹成為了一個嚴重的問題，因此，我們提出了兩種加速技巧：(1) 邊界案例重新排序及過濾(corner reordering and filtering) 和(2) 全局延遲時間約束(global delay constraint)。實驗結果顯示了比起MCSTA，MCFTA 平均減少了7% 的延遲時間以及在最佳的情況下減少了47% 的延遲時間。

Timing analysis on multi-corner becomes more important in modern VLSI design flow. In order to achieve a better timing closure, manufacturing process variations which lead to circuit timing variability should be taken into consideration. Multi-corner static timing analysis (MCSTA) was proposed to solve this problem. However, delays calculated by MCSTA are usually too pessimistic, as it evaluates circuit delays without taking false paths into consideration. In this paper, we propose a Multi-Corner timing analysis engine based on functional timing analysis (FTA) which can take false paths in to consideration and compute the worst-case delay more accurate than conventional static timing analysis (STA). However, as the number of process parameters grows, the expanding execution time of FTA becomes a serious issue. Therefore, two techniques: (1) Corner Reordering and Filtering (CRF) and (2) Global Delay Constraint (GDC), are proposed to speed up MCFTA. Experiment results show that the delay values reported by our MCFTA decrease 7% on average and 47% under the best case.