閘極環繞式多晶矽無接面奈米線薄膜電體的製作及其隨機電訊噪音的探討

Abstract

在這篇論文中，我們僅採用簡單而低成本的方法成功製備了環繞式閘極(GAA)多晶矽無接面奈米線薄膜電晶體。在製備的過程中，雖然我們只利用到I-Line的微影技術以及側壁蝕刻技術，但是所製備元件之奈米線通道長度和有效寬度可以分別達到120奈米和49奈米。由於奈米級元件尺寸和環繞式閘極的結構，元件的次臨界擺幅可達80mV/dec左右。也由於元件的尺寸足夠小，清晰的2層級隨機電訊噪音（RTN）也可以容易的觀察到。通過對不同氧化層陷阱(oxide trap)造成的2層級隨機電訊噪音進行分析，氧化層陷阱距離矽/二氧化矽界面的深度也被求出。我們更進一步發現了3層級隨機電訊噪音的存在，也對此訊號進行了分析。最後，我們提出了一種適用於多晶矽電晶體的RTN所造成的電流變化(ΔID/ID)的公式。

In this thesis, gate-all-around (GAA) poly-Si junctionless nanowire TFTs were successfully fabricated by using a simple and cost-effective method. In combination of I-Line-based lithography and spacer-assisted patterning techniques, nanowire devices with channel length as short as 120 nm and effective width of 49 nm were demonstrated. Due to the tiny nanowire channel and GAA structure, the devices perform low subthreshold swing (SS) down to 80mV/dec. Furthermore, clear RTN signals can be observed from the devices owing to the nanometer-scaled channel. Several 2-level RTN signals are shown in time domain and frequency domain, and the corresponding oxide trap depths from the SiO2/Si are extracted. Moreover, a 3-level RTN signals are also probed and analyzed. Finally, a new theory of ΔID/ID for poly-Si devices is proposed in this thesis.