氮化矽側壁硬式光罩方法製造環繞式閘極多晶矽奈米線電晶體之特性研究

Abstract

在本篇論文中，僅藉由I-Line微影技術成功製作出高度微縮之反轉式、堆疊式與無接面等操作形式之環繞式閘極多晶矽奈米線(nanowire)電晶體。透過源極/汲極側壁以及氮化矽側壁硬式光罩(nitride-spacer hardmask)的搭配，通道長度以及奈米線寬度可分別微縮至200奈米以及15奈米以下。本文並透過固相結晶法、固相結晶法加上後續離子佈植以及同步摻雜之低壓化學氣相沉積等技巧，分別形成多晶矽反轉式、堆疊式與無接面電晶體之無摻雜、低摻雜與高摻雜濃度之通道。由實驗所得低於100 mV/dec的次臨界擺幅以及可忽略的汲極引發勢壘降低，證實結合奈米線通道與環繞式閘極(Gate-All-Around)的元件所展現的良好閘極控制能力。另外，本文中亦討論三種不同類型的元件其基本電性的差異，以及隨通道長度的變異的特性變化。透過有效微縮的元件，可量得清晰的二層級隨機電報雜訊(2-level random telegraph noise)並進行分析，並進一步萃取不同偏壓下的特性常數，包含時間常數，以及隨機電報雜訊振幅，以研究二層級隨機電報雜訊的行為。

In this thesis, short-channel gate-all-around (GAA) poly-Si inversion mode (IM), accumulation mode (AcM), and junctionless (JL) NW transistors were successfully fabricated with I-Line-based lithography. In combination of source/drain-spacers and nitride-spacer hardmask, the channel length and the dimensions of NW cross-section can be effectively scaled to an extent smaller than 150 nm and 15 nm, respectively. In the fabrication, un-doped, moderately-doped, and in-situ doped poly-Si channel of IM, AcM, and JL devices, respectively, were formed by Solid-Phase-Crystallization(SPC), SPC and the following ion-implantation, and LPCVD. The utilization of tiny NW channels and of the GAA configuration allows the fabricated devices to exhibit excellent electrical characteristics in terms of small S.S. and negligible DIBL, evidencing the good gate controllability. The fundamental electric characteristics and the dependence of channel length of these three types of devices are also analyzed. With the effectively scaled devices, clear 2-level RTN can be measured and analyzed. RTN time constants and amplitude are extracted and analyzed to gain more insight into the switching properties.