前瞻性設計中解決性能及低功率議題的測試方法

Abstract

隨著製程技術不斷在縮小，晶片的飄移性在不同的製程步驟下卻沒有隨之縮小，像這樣的製程變異性，尤其是晶片內部的製程變異性，會導致生產出來的晶片在速度及耗能源的飄移性極大，為了要維持一個可接受的良率，一個測試的流程叫做速度分級是用來區分這些生產晶片到不同速度的群集藉由其可以達到的最高操作速度，以此去將不同品質的晶片以不同的價格來賣。這篇博士論文就是希望在先進製程下能解決因製程飄移所造成在速度性能上與低耗電上的議題。 因此我們可以將接下來的章節分成低耗電主題 (章節一與二)，以及速度性能主題 (章節三與四) 去做探討。 在章節一，我們提出一個單一測試訊號輸入的測試資料解密的架構，取名為STSD，其使用了技巧以複製測試資料切面來減少測試資料的容量，也同時減少了訊號的變異性在測試電路的路徑上。 STSD架構的編碼著重在去最大化測試資料切面的複製次數，以此減少測試時的能源損耗，我們更提出了個數學模型來評估其壓縮倍率、測試時間及輸入時的能源損耗，此數學模型可以幫助我們去決定最好的參數來設定STSD架構，使得我們不用去花費大量時間來做模擬評估。 在章節二，我們首先分析了使用粗質的複數閘門電壓的電路中的電流源開關架構，然後提出了方法來測試這些電流源開關使否有斷路錯誤，我們提出了一個特別為此設計的自動產生測試資料的演算法，來產生出一個會通過最長路徑且同時能盡可能產生訊號的變異性在我們目標的電流源開關周遭。 在章節三，我們提出了一個模型擬合的架構來連結在晶片上的環狀震盪器以及晶片可操作的最高速度，這個建構出來的模型可以使用在自動測試機台(auto test equipment) 軟體上，藉此來預測晶片速度來達成晶片速度分級，這樣的流程可以避免去使用大量的系統上測試，可以減少千倍以上的測試時間，其副作用為會將極為少量的晶片去擺放到較為保守的分級中，我們的實驗是建構在360個測試晶片在一個28奈米、0.9電壓及16GHz的手機晶片中。 在章節四，我們首先提出了一個模擬的環境來模擬晶片的最高操作速度及其環狀震盪器結果，這些模擬晶片是用來在我們提出的環狀震盪器擺放策略中使用，及驗證結果的效益，接著使用一個模型擬合的架構來連結在晶片上的環狀震盪器以及晶片可操作的最高速度，最後我們提出一個有效的方法來決定環狀震盪器的最佳擺放策略為了預測晶片最高操作速度。

As the device feature size keeps on scaling, the device variability imposed by each process step does not scale accordingly, leading to greatly increased process variations for advanced technology nodes. Such significant process variations, especially the intra-die variations, result in a wide spread of the performance for each manufactured chip. In order to maintain an acceptable yield without losing performance, a testing procedure called speed binning is applied to classify the manufactured chips into different bins based on their maximum functional speed on the system, denoted as Fmax, and then sell the chips with different prices according to the speed bin. This dissertation is focused on solving the performance and low-power issues caused by the process variation on advanced designs. Therefore, we can separate the following sections into two issues, low-power issue (Chapter 1 and 2), and performance issue (Chapter 3 and 4). In chapter 1, we presents a single-test-input test-decompression scheme, named STSD, which utilize the technique of test-slice duplication to reduce the test-data volume as well as the signal transitions along scan paths. The encoding of STSD scheme focuses on maximizing the number of duplications made by a test-slice template. Mathematical models are also developed in this section to estimate the compression ratio, test-application time, and scan-in transitions caused by STSD scheme, and in turn can further help designers to efficiently identify the best configuration of STSD scheme instead of going through a time-consuming simulation process. In chapter 2, we study the usage of coarse-grain MTCMOS power switches, and then propose methods of testing stuck-open power switches. A specialized ATPG framework is proposed to generate a longest possible robust test while creating as many effective transitions in the switch-centered region as possible. In chapter 3, we presents a model-fitting framework to correlate the on-chip measured ring-oscillator (OPM) counts to the chip's maximum operating speed (Fmax). This learned model can be included in an ATE software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and hence result in a 3-order test time reduction with a limited portion of chips placed into a slower bin compared to the conventional functional-test binning. The experiments were conducted based on 360 test chips of a 28nm, 0.9V, 1.6GHz mobile-application SoC. In chapter 4, we first propose a simulation framework to sample a chip's Fmax and it's OPM result. These samples are used to develop our methodology of OPM placement and to verify the effectiveness of an OPM placement. Then, a model-fitting framework is presented to correlate the OPMs' result to chip's Fmax. Finally, we propose a methodology to identify optimal placement of OPM for predicting Fmax.