使用晶片內部硬體製程監控器作速度分級之最佳化技巧

Abstract

在本篇論文中提出了使用晶片內部硬體製程監控器做速度分級之最佳化技巧, 我 們使用一個由修改SDF 技術以及模型建置所組成的流程來模擬晶片數據最終分析 我們應該要放多少的硬體製程監控器以及放在哪裡. 所提出的硬體製程監控器放 置處建議比貪婪方法有著更出色的表現, 在不同的製程變異下速度的平均誤差以 及最大誤差都至少有50% 的下降. 不同速度分級的方法也被提出並比較.

In this work, an optimization methodologies of using on-chip hardware process monitors for speed binning is proposed. A flow of composed of SDF-modifying technique and model-fitting framework is used to generate the simulated data and analysis where and how many should we place hardware process monitors. The proposed guide line for on-chip hardware process monitors placement shows better efficiency than greedy method. The mean error and maximum error is reduced over 50% in different parameter of process variation. A comparison of different method of speed binning is also presented. ii