通用繪圖處理器的設計與實作

Abstract

由於平行運算的興起，通用繪圖處理器已經成為提高處理器效能的重要加速器，本論文主旨為探討通用繪圖處理器之架構，並結合由AMD所主導的Heterogeneous System Architecture機構所定義的規範，建構出完整的異質多核心架構。Massive-SIMD Processor為本論文實作的一個通用繪圖處理器，論文中會詳細描述該指令集架構及處理器架構，並以暫存器傳輸級 (Register-transfer level, RTL) 實作於Xilinx Zynq-7020 FPGA開發版上，再配合HSA規範中的Packet Processor作為通用繪圖處理器之介面，使用者可以透過HSA Runtime API快速的控制繪圖處理器來加速運算。

Because of parallel computing, the General Purpose Graphic Processing Unit (GP-GPU) is the essential device to improve the performance of computing systems. We present the design of a heterogeneous system on an FPGA device with the Massive-SIMD Processor, the proposed General Purpose Graphic Processing Unit, and the supporting logics conforming to the Heterogeneous System Architecture (HSA) specifications. HSA makes it easier to program heterogeneous computing devices. In this thesis, the Instruction Set Architecture and Micro-architecture of the Massive-SIMD Processor will be presented and the implementation is based on register-transfer level verification on Xilinx Zynq-7000 SoC device. In addition, an HSA-compliant Packet Processor IP is presented and used as the interface between an ARM Cortex A9 processor and the Massive-SIMD Processor. The complete system is implemented and verified on a Xilinx Zynq 7020 programmable SoC device.