四核心Java處理器的架構改進

Abstract

本篇論文以四核心Java應用處理器JAIP-MP為基礎，將bus protocol從PLB搬到AXI4上，並針對四核心的JAIP處理器的提出兩種管理核心間維持共享資料一致性的元件，第一個是cache data coherence controller，使用broadcast機制來管理四個核心cache內的資料一致性，第二個是heap manager coherence controller，管理四個核心及RISC端對heap做記憶體管理的時候，維持heap上的指標的一致性及原子性，藉此對先前四核心JAIP的coherence機制做改進。在單核心方面，我們針對JAIP的cache存取提出三種加速的方法，第一個是建立field的lookup table，讓field存取在JAIP中能有更好的效率，第二個是讓JAIP在cache write時略過傳送訊號，減少JAIP的等待時間，第三個是對多執行緒的context switch做改進，減少cache存取跟context switch在JAIP內部產生的訊號衝突，利用這三種方法讓單核心JAIP得到更高效率的同時，也進一步的讓多核心JAIP獲得更高的效能。最後，我們還幫JAIP加入完整支援64-bit整數ALU及相關指令的元件，讓JAIP對Java語言規格的支援度更完整。

This thesis is developed based on a quad-core Java Application IP (JAIP-MP). We change the bus protocol from PLB to AXI4 and use two different controllers to solve the coherence problems, which appeared after the protocol modification. The first controller, cache data coherence controller, uses broadcasting mechanism to manage the coherence of the cache data between cores. The second controller is called the heap manager coherence controller, which manages the coherence and atomic of the heap allocation pointer while the heap was allocated by the JAIP cores or the RISC core. For the single core, we develop three methods to speed up accessing to the cache. The first method is to build a cache-like lookup table for field accessing. The second method is to reduce the cache stalled cycles while the cache is writing data back to the heap through the bus. The third method is to improve the mutex lock mechanism since cache accessing and the context switching will compete with each other, resulting a signal conflict while running a multithreading program. With these three methods, we gain much better efficacy in both single-core and quad-core JAIP. Finally, we add the component that completely supports 64-bit long type ALU and relative instructions to the JAIP in order to enhance the support of the Java language speculation in the JAIP.