標題: | VIFI-CMP: Variability-Tolerant Chip-Multiprocessors for Throughput and Power |
作者: | Lee, Wan-Yu Jiang, Iris Hui-Ru 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Process Variation;Chip-Multiprocessor;Monte Carlo Analysis |
公開日期: | 2009 |
摘要: | This paper proposes a new architecture of variability-tolerant chip-multiprocessor. To mitigate the impact of process variability on throughput and power, voltage and frequency islands are introduced into chip-multiprocessors. Thus, voltage island frequency island chip-multiprocessors enable per-core scaling on the supply voltage and operating frequency. It can naturally collaborate with dynamic voltage frequency scaling. The process variations are characterized through an analytical model, and are quantified through Monte Carlo analysis. Compared with the design without process variations, when 70 threads are run on a chip of 70 small cores, our results show throughput degradation is 0.06%, while power reduction is 36.27%. |
URI: | http://hdl.handle.net/11536/13945 |
ISBN: | 978-1-60558-522-2 |
期刊: | GLSVLSI 2009: PROCEEDINGS OF THE 2009 GREAT LAKES SYMPOSIUM ON VLSI |
起始頁: | 39 |
結束頁: | 44 |
顯示於類別: | 會議論文 |