用於高效率視訊編碼之快速背景分類可適性率失真最佳化

Abstract

在最新的影像編碼標準High Efficiency Video Coding中，更大的預測單位大小及更多方向的預測模式，使得在率失真最佳化(Rate Distortion Optimization)的計算複雜度大幅地提升；為了滿足即時編碼的需求，這篇論文提出了一種適用於硬體實現的快速率失真估測演算法以及相對應的硬體設計。 碼率估測的設計面臨很嚴重的資料相依性問題，而機率模型的更新以及記憶體資料的讀取也嚴重的影響吞吐量以及平行處理的可能性。因此，為了解決以上問題，我們採用資訊熵作法，但有別於之前對所有context groups整體做一次的計算，我們對於不同的context group個別計算其資訊熵，並依照其context group的特性以及各個TU 的大小調整個別估算的結果，可得到更準確結果。此外，我們也將我們的方法擴展到inter prediction而不像以前的方法只能處理intra prediction的部分。 至於在失真估測方面，我們則是藉由轉換矩陣維度(Transform-domain)取代原本的空間維度(Spatial-domain)來省去反離散餘弦變換(Inverse-Discrete Cosine Transform)與影像重建等部分。 在量化階段，我們對於 TU 大小為32x32以及16x16的高頻部分，採取固定零子區塊的做法，以降低量化階段的計算成本。這裡所提出的演算法在減少硬體花費的同時，也保證了編碼的品質，在BD-rate上平均僅有1.77%的增加。 在硬體設計上，採用基於4×4區塊由小而大的結構。此外，RDO採用亮度彩度交替式編碼來減輕資料相依性的問題。最後我們設計的硬體若以TSMC 40nm的技術合成，大約需要57.95K邏輯閘的數目量，而其可在工作頻率為400MHz的情況下，滿足處理畫面大小為4K×2K，每秒30張畫面的影片規格。

Various coding structures and modes in latest High Efficiency Video Coding (HEVC) standard lead to higher computation complexity of rate distortion optimization. To meet the real time demand, this thesis proposes a hardware-friendly Rate-Distortion Estimation algorithm and its hardware design. For rate estimation, the serious data dependency issues of rate estimation, probability update and memory accessing become a bottleneck to higher throughput and parallel processing possibilities. To solve these problems, we calculate the information entropy of each context groups and adaptively adjust the estimation result according to each context group characteristic and TU sizes instead of single estimation equation for all groups in previous approach. Besides, we also extend our approach from intra prediction to inter prediction instead of intra prediction only in other works. For the distortion estimation, we use the transform domain instead of spatial domain estimation to save inverse discrete transform computation and image reconstruction. The required quantization computation cost is reduced by adopting fixed zero sub-blocks in high frequency part for size 32x32 and 16x16. The proposed algorithm reduces required hardware cost while maintains low quality loss by hardware friendly algorithm modifications. With these modifications, the BD-rate loss is only 1.77% on average. The proposed hardware design adopts a 4×4 based bottom-up structure to fit different kinds of processing units. In addition, the RDO stage uses the Luma/Chroma interleaved coding schedule to lessen the effect of data dependency. The final implementation with TSMC 40nm CMOS process can achieve real time 4K×2K@30fps encoding with 57.95K gate count while operating under 400MHz clock frequency.