半導體蝕刻製程參數調整最佳化 –以P公司蝕刻製程為例

Abstract

在半導體晶圓製造過程中，製程需要三百多道手續，而在這些製程在蝕刻製程後都有一定的圖案的大小，稱為臨界尺寸(Critical Dimension，CD)。CD的大小及變異對於最終產品品質很重要，其中在閘極蝕刻製程後的CD又顯得格外的重要，因為它肩負著一塊積體電路正常運作與否的關鍵。因此本研究針對個案公司的閘極蝕刻製程加以研究，以控制閘極蝕刻製程後其中一個關鍵圖案，Memory cell的CD為目標，利用實驗設計與反應曲面法找出該製程的關鍵因子與最佳設定值，使其能以快速且有效的方式下調整閘極蝕刻製程的參數設定。本研究論文最後以台灣某半導體廠提供之閘極蝕刻製程的實際資料，驗證了本研究方法確實可以快速有效控制製閘極製程後的CD大小及穩定性。

There are around 300 producing process in the entire semiconductor wafer fabrication. Critical Dimensions shown on the resulting pattern after the etching process are very important to the quality of the final product since they are the key to determine whether the integrated circuits function as designed. In this research, the gate etching process of the case company, a Taiwan semiconductor fabricator, was studied. The main focus was on the control of the Memory cell CD measured after the gate etching. Design and Experiments and response surface method were utilized to effectively identify the key factors along with their settings in the process to optimize the CD of the memory cell. Real data provided by the case company was used to verify the effectiveness and efficiency of the proposed method. It is found that the settings found by this study can effectively control the size the stability of the CDs in Memory cell.