應用實驗設計法降低預燒製程Pretest不良率-以Z公司為例

Abstract

隨著半導體製程技術不斷的提升以及電子產品市場多元化的需求下， IC晶片以多功能性、體積小、重量輕、高I/O及散熱佳等方向來設計與製造。位處於半導體後段製程的IC測試廠算屬服務業，此乃因IC測試廠並不製造產品，而是將客戶或上游封裝完成的IC成品透過専業的機器設備檢測產品的良窳及等級，並及時將測試結果反應給上游或客戶以作為製程改善和調整之依據。因此如何精確並有效的測試IC成品是所有IC測試廠相當重視的一個議題。本論文所探討的是記憶體IC在測試流程中的預燒製程，研究目的是有效降低Pretest不良品的產生，進而降低Pretest不良率。本研究規劃了一個2K實驗設計(Design of Experiments, DOE)篩選出影響預燒製程之Pretest 不良的顯著因子，再針對篩選出的關鍵因子，利用反應曲面法(Response surface methodology, RSM)來分析製程，以找出製程之最佳參數組合。本研究最後以台灣某半導體封裝測試廠為實證，來說明本研究確實有效。

As the results of the improvement of the technology in semiconductor process and the marketing demand for multi-functional electronic products, the design of Integrated Circuits（IC）chips tends to be smaller, lighter, high I/O, multi-functions, and have efficient heat exhausting. In the backend of semiconductor manufacturing process, an IC testing house is considered as a service industry. It receives IC chips from the customers or assembly houses and measures the IC using the professional machine and equipment to identify whether the IC is good or fail and to determine the IC quality grades. Therefore, how to probe IC precisely and efficiently is a very important issue for all testing houses. This study focused on reducing the pretest failure rate of IC. Consequently, the pretest failure rate of Memory IC in Burn-In process will be effectively reduced during testing flow. In this study, the Design of Experiments (DOE) is utilized to explore the major root causes or factors of the Pretest failure problem before Burn- in process. Analysis of variance was applied to analyze the experimental data. Then, the Response surface methodology (RSM ) is employed to determine the optimal values for parameter setting. Finally, a real case provided by an IC testing company in Taiwan is utilized to demonstrate the effectiveness of the proposed method.