奈米Si CMOS元件模型與參數萃取方法應用於包含佈局與應力工程效應之高頻模擬與雜訊分析

Abstract

本論文之研究主題涵蓋多閘指CMOS元件以及嵌入式SiGe（e-SiGe）應變P-MOSFETs元件。這兩種元件都是以奈米級Si CMOS製程實現之，且針對高頻以及高速電路與系統的應用。其中，多閘指CMOS元件有著複雜的佈局相關效應，因而在高頻特性以及射頻雜訊模擬方面帶來很大的挑戰，此為多閘指CMOS元件應用於射頻以及類比電路設計的關鍵性問題。至於在嵌入式SiGe應變P-MOSFETs元件部分，其雖能提升遷移率而有利於高速電路應用本論文之研究主題涵蓋多閘指CMOS元件以及嵌入式SiGe（e-SiGe）應變P-MOSFETs元件。這兩種元件都是以奈米級Si CMOS製程實現之，且針對高頻以及高速電路與系統的應用。其中，多閘指CMOS元件有著複雜的佈局相關效應，因而在高頻特性以及射頻雜訊模擬方面帶來很大的挑戰，此為多閘指CMOS元件應用於射頻以及類比電路設計的關鍵性問題。至於在嵌入式SiGe應變P-MOSFETs元件部分，其雖能提升遷移率而有利於高速電路應用，但同時也產生較大的閃爍雜訊（flicker noise），而對於低雜訊電路設計造成不利影響。這兩個主題不論是在元件特性分析，參數萃取，模型建立以及高頻與低雜訊最佳化設計等方面，都帶來了嚴峻的挑戰。 利用60nm高效製程完成之e-SiGe應變P-MOSFETs元件，能夠有效提升電洞遷移率高達75%，且同時等比例增強了通道電流（IDS）以及轉導（gm）。然而，此單軸壓縮應變力同時也導致了閃爍雜訊的增加，高達80%。遷移率變動模型(mobility fluctuation model)能夠合理解釋量測所得之閃爍雜訊特性，且其預測與實測相當一致。再者，遷移率變動模型分析顯示，應變P-MOSFETs元件呈現較大之H (Hooge參數)，乃是導致閃爍雜訊增加的主要因素。本論文中所提出的順向偏壓方法，經由實測已證明能夠同時改善遷移率以及閃爍雜訊特性，且不須採用應變製程而為一低成本的方法。 針對多閘指MOSFET元件，由淺溝槽隔離區（STI）產生之應力，淺溝槽頂端邊緣圓角結構(STI TCR)三維雜散電容以及電阻等，均包含微妙且複雜的佈局相關效應；對於等效遷移率(eff)、等效閘極寬度(Weff)、轉導(gm)、閘極側壁電容(Cof)以及閘指端雜散電容(Cf(poly-end))等基本的元件參數造成直接影響。上述效應對於高頻特性以及射頻雜訊特性參數，例如截止頻率（fT）、最大震盪頻率（fMAX）、最小雜訊指數（NFmin）以及等效雜訊電阻（Rn）等，造成利與弊不一致的影響，因而難以兼顧所有參數達到同時最佳化。尤其甚者，目前大多數應用於CMOS電路模擬之元件模型，包含最廣泛使用之BSIM4（3），均無法正確模擬佈局相關效應，而在I-V, C-V, 高頻以及射頻雜訊的模擬上呈現諸多問題。並且，其模擬誤差，隨著元件微縮以及應用頻率的提升而愈益嚴重。 針對前述問題，本論文首次提出一個新穎的元件參數萃取方法（美國專利號8,691,599 B2），利用高頻S參數，改良的開路去寄生效應技術，以及Raphael模擬等方法下，能夠準確地萃取出閘極長度Lg，閘極介電層等效電容Cox(inv), 以及由STI TCR所產生的W等關鍵元件參數，以準確萃取等效遷移率(eff)，並修正本質MOSFET模型參數。針對高頻模擬，我們結合了本質雜散電阻、電容與電感以及基極網路(body network)之電阻、電容與電感，建立了改進的MOSFET元件模型，可以針對不同佈局的多閘指MOSFET元件，正確模擬其經去寄生效應後所得之本質S參數以及Y參數。此外，改進的MOSFET元件模型包含本質雜散電阻所得之模擬結果，相較於理想的本質MOSFET元件模型為基準點，可以有效檢驗閘極電阻Rg,萃取值之準確性，以及其佈局相關效應對於fMAX, NFmin, 以及 Rn的影響。 最後，藉由結合改進的MOSFET元件模型以及本實驗室已驗證完成之損耗基板模型(lossy substrate model)，得以建立完整的等效電路模型，以準確模擬量測所得且未經去寄生效應之高頻S參數、Y參數以及雜訊參數。再者，損耗基板去寄生效應方法(lossy substrate deembedding method)，可應用於多閘指MOSFET元件以準確萃取其本質雜訊。相較於傳統採用之雜訊相關矩陣(noise correlation matrix)來萃取本質雜訊的方法所存在的變異過大問題，此損耗基板去寄生效應方法不僅能有效降低變異，還能準確反應出本質特性的佈局相關效應。本論文首創的元件參數萃取方法以及高頻元件模型，能夠促進奈米射頻CMOS元件佈局最佳化設計，以達到提升高頻效能與降低雜訊之設計目標。

In this thesis, the research topics cover the multi-finger CMOS devices and embedded SiGe (e–SiGe) strained p-MOSFETs, both of which were fabricated in nanoscale Si CMOS technologies and aimed at high frequency and high speed applications. The former reveal complicated layout dependent effects and bring significant challenges to high frequency and RF noise simulation for RF and analog circuits design. The later can yield mobility enhancement for higher speed but may impose penalty on low noise circuits design due to increased flicker noise. Both topics introduce stringent challenges to the devices characterization, parameters extraction, modeling, and optimization for high frequency and low noise design. The e-SiGe strained pMOSFETs implemented in 60nm high performance technology, can contribute 75% higher effective mobility (eff) and proportional enhancement in the channel current (IDS) as well as transconductance (gm). However, this uniaxial compressive strain leads to more than 80% higher flicker noise. Mobility fluctuation model can consistently explain the measured flicker noise and the increase of Hooge parameter (H) is identified as the key factor responsible for the increase of flicker noise in the strained pMOSFETs. The forward body biases (FBB) proposed in this thesis is proven an effective solution for simultaneous improvement of eff and flicker noise, and cost reduction without resort to strain engineering. For the multi-finger MOSFETs, the subtle layout dependent effects contained in the STI stress, STI top corner rounding (TCR), 3-dimensional parasitic capacitance and resistances introduce direct influence on the basic device parameters, such as eff, Weff (effective width), gm, Rg (gate resistance), Cof and Cf(poly-end) (gate sidewall and finger-end fringing capacitances). The mentioned effects lead to complicated trade-offs between the high frequency performance and RF noise parameters like fT (cut-off frequency), fMAX (maximum oscillation frequency), NFmin (minimum noise figure), and Rn (equivalent noise resistance), etc. Unfortunately, most of the compact CMOS models including BSIM-4(3) cannot accurately simulate the layout dependent effects and expose the problems through the I-V, C-V, high frequency, and RF noise simulation. The deviations become particularly large when down-scaling the devices and increasing the frequencies. For the first time, in this thesis, a novel device parameters extraction method (US patent 8,691,599 B2) based on high frequency S-parameters, an improved open deembedding technique, and Raphael simulation, has been developed for precise determination of the key device parameters like Lg, Cox(inv), and STI TCR induced W to realize accurate extraction of eff and the calibration on the intrinsic MOSFET model. As for high frequency simulation, an improved MOSFET model incorporating intrinsic parasitic RLC and body network RLC model, has been established with high accuracy certified by a good match with the intrinsic S- and Y- parameters after deembedding, and the scalability over multi-finger MOSFETs with various layouts. Also, the simulation by the improved MOSFET model compared to the ideally intrinsic MOSEET model can facilitate accurate extraction of Rg, and the layout dependent effects in fMAX, NFmin, and Rn. Finally, the improved MOSFET model combined with our proprietary lossy substrate model build up a full equivalent circuit model, which can accurately simulate the measured S-, Y- and noise parameters prior to deembedding. Furthermore, the lossy substrate deembedding method can be applied to the multi-finger MOSFETs as a reliable solution for intrinsic noise extraction, which can eliminate the problems of conventional noise correlation matrix method and successfully identify the layout dependent effects in the truly intrinsic characteristics. The new methods for parameters extraction and modeling achieved in this thesis can facilitate RF CMOS devices layout optimization for high frequency and low noise design.