使用多級延遲切換機制之時間數位轉換器之全數位鎖相迴路

Abstract

在物聯網及5G的呼聲越來越高，前景越來越被看好的情況下，個人化和系統化的晶片設計(SOC)的重要性也隨著提升。鎖相迴路－作為一個SOC設計上占有重要的一席之地的電路，廣泛的被使用在時脈資料回復電路、無線通訊系統收發器等相關應用上。早期鎖相迴路電路以類比式架構為主，不同區塊間的信號皆以類比的方式進行傳遞，分析上則採用拉普拉斯(Laplace)轉換後的頻域來進行分析。以設計的觀點來看，複雜度算低。在較長的產品生命週期及無功率消耗的考量下，傳統類比式的鎖相迴路可足以應付所面臨到的所有應用。然而，隨著可攜式裝置的市場逐漸增大、製程技術日趨的成熟，數位式鎖相迴路電路之優點和需求逐漸被彰顯出來，展露出取代類比式之姿。由於信號的傳輸採用數位的方式進行，數位式鎖相迴路表現出較高的抗雜訊能力。另外若電路採用全數位的架構，電路即可跟著製程的微縮，無須再另行設計，這對於現在產品週期短的趨勢上來說，是數位電路的一大優點。除此之外，類比電路中使用到的被動元件耗費較多的面積，操作速度上也比數位電路速度慢的許多。綜合以上幾點原因，近年關於鎖相迴路的研究中，全數位鎖相迴路占了相當大的一塊比例。 本篇論文以全客戶式設計完成全數位式鎖相迴路，第一顆晶片提出一種具有多級延遲切換機制的時間數位轉換器。其可偵測電路的相位鎖定狀態，判斷是否需進行模式的切換，進而選擇對整體電路最有利的轉換延遲時間。第一顆晶片中採用週期線性的環形數位控制振盪器，振盪頻率範圍可涵蓋130MHz~1.22GHz。第二顆晶片以第一顆晶片作為電路基礎，再加入時間放大器和最高位元偵測器，使時間數位轉換器具有更高的解析度和更低的功率消耗。 所提出的兩顆晶片皆將輸出頻率鎖定至800MHz；第一顆晶片的量測結果，時脈抖動為36.67ps的峰對峰值時間抖動(Peak to Peak jitter)，功率消耗為17.5mW，核心面積為0.1088mm2。而第二顆晶片的模擬平均峰對峰值時間抖動(Peak to Peak Jitter)為13.6ps，功率消耗為9.1mW，核心面積為0.0694mm2。

As the Internet of Things (IOT) and 5G applications become more and more popular, the importance of full-customer and the SOC design increases as well. Phase-Locked Loops (PLLs), as one of the key parts in SOC designs, are widely used in the Clock and Data Recovery (CDR) and wireless communication systems. In the early development of PLLs, the designs were realized by analog approach. Continuous-time signals are transferred among different blocks and the whole system is analyzed the in frequency domain, which can be derived through the Laplace Transformation. From the prospect of the design complexity, the analog PLL (APLL) is a good choice because it requires less complexity. During the time when the product has long Life-Cycle, traditional analog PLLs are capable to deal with almost all diversity of applications. However, as the number of portable devices grows and the process technology advances, the advantages of all digital PLLs (ADPLLs) are gradually discovered and also reveals that it has the penitential to replace the APLLs. Because the signals transferred between each two blocks are digital values (0 or 1), a DPLL provides better performance in anti-noise ability. If a system is realized through digital circuit implementation, then there is no need to redesign with the process technology scaling down, which brings a brilliant merit in designing short-life-cycle products. Moreover, analog PLL circuits use passive components, which occupy lots of area, and the speed of analog PLL circuits is usually slower than that of digital PLL circuits. Therefore, the discussions about all-digital phase-locked-loops (ADPLLs) take up a large proportion of phase-locked-loop researches. In this thesis, we implement ADPLLs by using full-custom design flow. For the first chip, we propose a time-to-digital converter with multiple-delay switching mechanism which can detect the phase-locked state and decide the optimized delay path according to the detected state. The proposed DCO with a linearly periodic digital-to-frequency relationship operates from 130MHz to 1.22GHz. For the second chip based on the first chip, a Time Amplifier (TA) and a Most-Significant-Bit (MSB) detector are introduced to achieve higher resolution and lower power consumption for the proposed TDC. Both of chips are designed to lock at 800MHz. The measurement results show that the first chip has a peak-to-peak jitter of 36.67ps. The area of the core circuit in ADPLL is 0.1088mm2, and the power dissipation is 17.5mW. For the second chip, the post-simulation shows the value of the peak-to-peak jitter is 13.6ps, and the power dissipation is 9.1mW. The core circuit occupies the area of 0.0694 mm2.