內嵌次臨界參考電壓源之0.5V無電容式低壓降線性穩壓器

Abstract

近年來隨著可攜式行動裝置的蓬勃發展，要如何開發體積小且低功耗的晶片，以有效使用有限的電池能量成為首要的課題。因此本論文提出低電壓無電容式低壓降線性穩壓器，並內嵌次臨界CMOS參考電壓電路以摒除需外部輸入參考電壓，如此一來可作系統化應用。 傳統低壓降線性穩壓器需要外部電容來抑制暫態響應並串聯電阻來補償頻率響應，但極零點會隨著負載變動而異，使串聯電阻補償方式變的複雜。同時為了達到低功耗的要求，本論文低壓降線性穩壓器所使用的誤差放大器將操作在次臨界區，並利用數位方式控制五組不同大小的輔助功率電晶體來調節暫態響應，彌補誤差放大器頻寬的不足。本論文使用聯電0.18微米CMOS製程，晶片使用總面積為0.457×0.457mm^2。輸入電壓範圍為0.6V-1V，輸出電壓0.5V，最大負載電流為1mA。在0.6V操作電壓下，靜態消耗功率為8.25μW。

With the portable battery-operated device development. In order to effectively use limited battery, designing smaller and lower power chip become more important. Therefore, this thesis introduces low voltage capacitor-less low-dropout linear regulator (LDO). Meanwhile, with subthreshold CMOS voltage generator on chip, there is no need to import external reference voltage. As a result, the proposed LDO is suitable for systematic application. Conventional LDO requires external capacitor for transient response and equivalent series resistor (ESR) for frequency compensation. But it is hard to maintain because the location of output pole varies with load conditions. In order to achieve low power target, using error amplifier which is operating in subthreshold region for LDO. Through digitally controlling five different size auxiliary power MOSFETs to regulate transient response. Auxiliary power MOSFETs solve not only transient problem but also narrow bandwidth of error amplifier. The proposed chip in this thesis were fabricated using a standard UMC 0.18μm 1P6M CMOS process. Total area is 0.457×0.457〖mm〗^2. Output voltage is 0.5V, and input voltage range is 0.6V to 1V.