可適性調整相位邊限之電流回授補償技術應用於無電容式低壓降線性穩壓器

Abstract

隨著可攜式設備的蓬勃發展，為了有效使用分配有限的電池能量，電源管理系統是不可或缺的一環。低壓降線性穩壓器具有架構簡單、低雜訊、低成本的優點，對於電源管理晶片系統來說，低壓降線性穩壓器是一個非常重要而且廣泛應用的單元。 傳統低壓降線性穩壓器利用外部電容串聯寄生電阻補償，然而增益及極點位置隨負載變動，使得寄生電阻補償方式更顯得複雜。近年來，對於高效能(高精準度、高電源排斥比)之線性穩壓器需求越來越大，多級放大器之線性穩壓器恰可達到這個需求。同時，隨著系統單晶片的發展，無電容式之線性穩壓器逐漸受到重視。由於不需要外掛電容，電路板面積可大幅縮減，成本也大為降低。然而多級放大器之線性穩壓器的缺點是有最低負載的限制，導致無載時的功率耗費。 本論文將提出一可適性調整相位邊限之電流回授補償技術應用於無電容式低壓降線性穩壓器，此電流回授補償技術可可適性調整相位邊限在60°左右以達到快速之暫態反應能力。同時，在不犧牲頻寬之情況下，最低負載限制大幅降低至50μA。此外，電流回授補償技術使用與品質因素降低技術相當的補償電容，但電流回授補償技術可維持高的電源排斥能力頻寬。本論文使用TSMC 0.35μm2P4M製程，補償電容僅需5pF以及1.5pF。實驗結果顯示，最低負載限制大幅降低至50μA，而具可適性相位控制之低壓降線性穩壓器之暫態反應時間小於4μs。

With the increasing demanding of portable devices, how to use the battery energy efficiently is the most concerned problem. Therefore, power management system is indispensable for modern consumer products. For power management system, low-dropout (LDO) liner regulator is the most common block due to the characteristics, such as simplicity, small board space, low noise and cost. Conventional LDO regulator is compensated by the equivalent series resistor (ESR). However, this kind compensation is hardly to maintain because gain and poles locations are varied with load conditions. In recent years, the demanding for high performance liner regulator such as high load regulation and high power supply rejection is getting growing. The Multi-stage LDO can achieve this target. Meanwhile, with the development of SoC system, a capacitor-free LDO is preferred to reduce the board space and cost greatly. However, the most important disadvantage of multi-stage LDO is the minimum load restriction. Therefore, a current feedback compensation (CFC) technique for capacitor-free LDO regulators with adaptively adjusting the phase margin is proposed in this thesis. CFC technique can adaptively adjust the phase margin for achieving better transient response than that with variant phase margin at different load current conditions. Not only fast transient response is attained due to suitable phase margin but also the minimum load current limitation can be greatly reduced to about 50μA without sacrificing bandwidth at light load current condition. Besides, CFC technique can have high PSRR bandwidth with compatible compensation capacitors compared to the Q-reduction technique. The capacitor-free LDO regulator with CFC technique is fabricated by TSMC 0.35μm 2P4M CMOS process with small compensation capacitors 5pF and 1.5pF. Experimental results demonstrate that the minimum load can be reduced to 50μA and transient response time with adaptively phase margin control is smaller than 4μs.