60GHz毫米波系統之同頻同時全雙工設計與效能評估

Abstract

在本論文中提出了針對60GHz頻帶應用的同頻同時全雙工、正交分頻多工模組數位基頻接收器設計。此數位基頻接收器兼容於IEEE 802.15.3c和IEEE 802.11ad規格中之單一載波和正交分頻多工雙模式。此設計是根據IEEE 802.15.3c和IEEE 802.11ad規格，包含傳送端頻域自干擾消除、卷積修正向量模組、全數位同步模組、通道等化器、高吞吐量快速傅利葉轉換和相位雜訊消除器的數位基頻接收器。為了滿足可適用於2.64 GHz取樣率，本文所提的數位基頻接收器設計採用八倍平行且無反饋追踪路徑的設計。 為了設計同頻同時全雙工系統，合作夥伴同濟大學先進行60GHz頻帶的自干擾通道量測。量測結果指出，細波束指向天線可以有效的抑制自干擾的直接傳遞，但是近端反射影響增加通道的方均根延遲擴展。為了因應自干擾通道長時延遲擴展，我們提出一個低複雜度的傳送端頻域自干擾消除架構和卷積修正向量模組。卷積修正向量模組是由兩組64點濾波器以及24*144大小的記憶體所組成，其目的為修正頻域自干擾模組中循環卷積所造成的誤差項，同時可支援高達128點的自干擾通道。我們提出的傳送端頻域自干擾消除架構只需要一般時域自干擾消除面積的13.3%，而晶片面積和功耗分別佔整個接收器的20%以及12%。 如果自干擾能完全消除的情況下，以我們所提出的框架結構可以提升頻譜效率至原本的1.95倍。

In this thesis, a co-time co-frequency full duplex (CCFD) on SC-OFDM dual mode baseband receiver system for 60GHz application is proposed. The CCFD dual-mode digital baseband receiver based on the IEEE 802.15.3c and 802.11ad is composed of transmitter frequency domain digital interference cancellation (TX FD DIC) architecture, correction vector for convolution (CVC), synchronization, channel equalization, high throughput Fast Fourier Transform (FFT) and phase noise cancellation (PNC). In order to ease the clock rate, the modules of the digital baseband are designed with 8X-parallelism without a feedback loop to meet the 2.64 GHz sampling rate. For the design of CCFD, a real channel measurement is performed by Tongji University to characterize the self-interference (SI) channel in 60 GHz band. The results show that the narrow beam antennas can effectively suppress the direct leakage component but increase the near end reflection and thus increase the root-mean-square (RMS) delay spread of the SI channel. With the SI cancellation is required to support SI channel with large RMS delay spread, a low-complexity architecture of TX FD DIC is proposed with CVC which remedies the error term caused by FD DIC. The CVC is composed of two sets of 64-tap FIR filter and 24*144 memory to correct the head and tail invasion due to circular convolution and can support the channel length up to 128 samples. As a result, the hardware cost of the proposed TX FD DIC is only 13.3% of the conventional TD DIC with the same performance, and it accounts for 20% and 12% of the area and power consumption in terms of the whole system. An efficient frame structure is also adopted to raise the spectral efficiency to 1.95 times if the SI is all removed.